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Adventurer
Adventurer
1,172 Views
Registered: ‎01-19-2018

In MIG 7 series IP, ddr3_addr width changed in Vivado 2018.3

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Hello,

Until 2018.2, the address bus width was 16 bits.

Today I upgraded to 2018.3 and after IP upgrade, found that the ddr3_addr size is reduced to 15 bits.

Has this been done intentionally?

 We had some custom 'Memory Part' which we do not see in the drop-down for the MIG IP gen GUI flow.

Excerpt from the ip_upgrade.log

Upgrade Log for IP 'mig_7series_0'

1. Summary
----------

CAUTION (success, with warnings) in the upgrade of mig_7series_0 from xilinx.com:ip:mig_7series:4.1 to xilinx.com:ip:mig_7series:4.2

After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required.

2. Interface Information
------------------------

Detected external interface differences while upgrading 'mig_7series_0'.


-Upgrade has added interface 'CLK_REF_I' (xilinx.com:signal:clock:1.0)


3. Connection Warnings
----------------------

Detected external port differences while upgrading 'mig_7series_0'. These changes may impact your design.


-Upgraded port 'ddr3_addr' width 15 differs from original width 16

-Upgrade has added port 'clk_ref_i'

-Upgrade has added port 'device_temp_i'

 

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Moderator
Moderator
726 Views
Registered: ‎02-11-2014

Re: In MIG 7 series IP, ddr3_addr width changed in Vivado 2018.3

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Hello @gin_xil,

The Answer Record including a patch is now public and can be found here: https://www.xilinx.com/support/answers/71898.html. The issue will be natively fixed in the next major release of Vivado.

Please unmark the previous response as a solution and then mark this response as a solution so we can distribute the patch more thoroughly on the forums.

Thanks,
Cory

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11 Replies
Moderator
Moderator
1,145 Views
Registered: ‎02-11-2014

Re: In MIG 7 series IP, ddr3_addr width changed in Vivado 2018.3

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Hello @gin_xil,

Could you please provide your XCI/PRJ files you had in 2018.2 so I can run some tests for you? I ran a quick test with a 2018.2 7-series MIG with a custom part, upgraded it in 2018.3 and I ran into no issues in the upgrade flow.

Typically the way I migrate 7-series MIG (if I run into any weird issues in the flow) is by doing the following:

//create a new 7-series MIG IP in Vivado 2018.3
create_ip -name mig_7series -vendor xilinx.com -library ip -module_name mig_7series_0

//Associate mig.prj from 2018.2 IP with 2018.3 IP
set_property CONFIG.XML_INPUT_FILE {/path/to/mig/dot/prj/mig.prj} [get_ips mig_7series_0]

This should allow your custom part to stick in the IP.

Thanks,
Cory

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Adventurer
Adventurer
1,124 Views
Registered: ‎01-19-2018

Re: In MIG 7 series IP, ddr3_addr width changed in Vivado 2018.3

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@coryb,

Thanks for your reply.

I have attached the ZIP file for the MIG IP from the Vivado 2018.2 version.

This version is working fine after the Vivado upgrade to 2018.3.

Just now I tried your TCL way to upgrade. But here too the ddr3_addr is 15 bits.

 

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Moderator
Moderator
1,096 Views
Registered: ‎02-11-2014

Re: In MIG 7 series IP, ddr3_addr width changed in Vivado 2018.3

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Hello @gin_xil,

I am a bit confused by your last statement. The attached XCI file is working fine in 2018.2 and fine in 2018.3 after upgrade?

Thanks,
Cory

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Adventurer
Adventurer
1,016 Views
Registered: ‎01-19-2018

Re: In MIG 7 series IP, ddr3_addr width changed in Vivado 2018.3

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@coryb,

Sorry about this statement - This version is working fine after the Vivado upgrade to 2018.3.

It is wrong. It is not working after the upgrade. In 2018.2 it is working fine.

I have also tried your TCL way of upgrade. It is also not working in this method.

btw - Did you have time to analyze the XCI?

 

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Moderator
Moderator
964 Views
Registered: ‎02-11-2014

Re: In MIG 7 series IP, ddr3_addr width changed in Vivado 2018.3

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Hello @gin_xil,

I was able to reproduce your issue using a UCF and DDR3 configuration from https://forums.xilinx.com/t5/Memory-Interfaces/MIG-v4-2-Vivado-2018-3-pin-out-validation-is-too-strict-amp/m-p/924245#M13639.

I am working on putting together an Answer Record with a solution for this. Please hang tight till I can get it approved.

Thanks,
Cory

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Adventurer
Adventurer
943 Views
Registered: ‎01-19-2018

Re: In MIG 7 series IP, ddr3_addr width changed in Vivado 2018.3

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@coryb,

Thanks!

I will wait for your next messages.

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Moderator
Moderator
862 Views
Registered: ‎02-11-2014

Re: In MIG 7 series IP, ddr3_addr width changed in Vivado 2018.3

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Hello @gin_xil,

I have sent you an EZMOVE package including a 2018.3 patch. After you unzip the attachment, please take a quick peek at the readme. It explains 3 different install methods. Pick the one that works for your setup.

Let me know if you have any other issues.

Cory

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Adventurer
Adventurer
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Registered: ‎01-19-2018

Re: In MIG 7 series IP, ddr3_addr width changed in Vivado 2018.3

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@coryb,

Thanks and I have successfully downloaded it.

I will get back to you once I am able to use it.

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Adventurer
Adventurer
829 Views
Registered: ‎01-19-2018

Re: In MIG 7 series IP, ddr3_addr width changed in Vivado 2018.3

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@coryb,

The MIG core can now be successfully upgraded using the Xilinx patch and following instruction_1.

It seems to be working fine.

 

FYI - From the instructions txt file inside the zip file, this link Answer Record: http://www.xilinx.com/support/answers/71898.htm is not working.

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Moderator
Moderator
815 Views
Registered: ‎02-11-2014

Re: In MIG 7 series IP, ddr3_addr width changed in Vivado 2018.3

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Hello @gin_xil,

Thank you for verifying that the issue is resolved using the patch.

The link in the readme to Answer Record 71898  will not currently go anywhere. I am working on getting the AR pushed public as soon as possible.

Thanks,
Cory

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Moderator
Moderator
727 Views
Registered: ‎02-11-2014

Re: In MIG 7 series IP, ddr3_addr width changed in Vivado 2018.3

Jump to solution

Hello @gin_xil,

The Answer Record including a patch is now public and can be found here: https://www.xilinx.com/support/answers/71898.html. The issue will be natively fixed in the next major release of Vivado.

Please unmark the previous response as a solution and then mark this response as a solution so we can distribute the patch more thoroughly on the forums.

Thanks,
Cory

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