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whitleda
Contributor
Contributor
7,671 Views
Registered: ‎11-21-2013

Incorrect CS_N Width for Dual-rank DDR3

Currently getting the following error when trying synthesize MIG for a dual-rank SODIMM:

 

[Synth 8-549] port width mismatch for port 'c0_ddr3_cs_n': port width = 2, actual width = 1 ["E:/work/HDL/trunk/FDK/projects/XPedite2500/MIG/MIG.srcs/sources_1/bd/design_1/hdl/design_1.vhd":87]

 

I see the other control signal widths are at 2 as expected but it appears CS_N still only has a width of 1.  Appears to be a bug in the MIG block.

 

CS_N.png

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yenigal
Xilinx Employee
Xilinx Employee
7,667 Views
Registered: ‎02-06-2013

Hi

 

Which version of MIG and Vivado are you using?

 

Is this issue seen with example design of MIG also when generated from IP catalog also or only seen with block design.

Regards,

Satish

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whitleda
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Registered: ‎11-21-2013

Vivado 2014.4.1

MIG 6.1

 

Only seen in block design.

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