03-10-2015 12:34 PM
Currently getting the following error when trying synthesize MIG for a dual-rank SODIMM:
[Synth 8-549] port width mismatch for port 'c0_ddr3_cs_n': port width = 2, actual width = 1 ["E:/work/HDL/trunk/FDK/projects/XPedite2500/MIG/MIG.srcs/sources_1/bd/design_1/hdl/design_1.vhd":87]
I see the other control signal widths are at 2 as expected but it appears CS_N still only has a width of 1. Appears to be a bug in the MIG block.
03-10-2015 12:41 PM
Which version of MIG and Vivado are you using?
Is this issue seen with example design of MIG also when generated from IP catalog also or only seen with block design.