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Adventurer
Adventurer
8,145 Views
Registered: ‎03-02-2015

Incrementing app_addr

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Hi,

 

This is a basic question regarding MIG.The signal app_addr that we are giving to MIG,why are supposed to do "+ 8"  to the previous address location to get the next address location.

For example for the first data word if my app_addr is 8,then for 2nd data word i'm giving addr as 16.

 

Why are incrementing by 8 ?

My design is working alright,but i just wanted to know why we are doing this +8 to get to the next address location.

 

Thanks

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Xilinx Employee
Xilinx Employee
14,948 Views
Registered: ‎07-11-2011

Hi, 

 

Generally you need to tie the lower address bits [2:0] to zero to accomplish burst addressing of DDR3.

so you need to increment in 8, 16, 24, 32 etc or in multiple of 8

 

Please refer below ARs to know more about address map and address increment options 

http://www.xilinx.com/support/answers/33698.html

 

http://www.xilinx.com/support/answers/34779.html

 

Hope this helps

 

 

-Vanitha.

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Xilinx Employee
Xilinx Employee
14,949 Views
Registered: ‎07-11-2011

Hi, 

 

Generally you need to tie the lower address bits [2:0] to zero to accomplish burst addressing of DDR3.

so you need to increment in 8, 16, 24, 32 etc or in multiple of 8

 

Please refer below ARs to know more about address map and address increment options 

http://www.xilinx.com/support/answers/33698.html

 

http://www.xilinx.com/support/answers/34779.html

 

Hope this helps

 

 

-Vanitha.

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Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

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Adventurer
Adventurer
8,134 Views
Registered: ‎03-02-2015

@vsrunga:

 

Suppose for the sake of argument my DDR chip has only 800 address locations & if i'm doing + 8 to get to the next address then am i only able to access only 100 of those locations or those 800 locations are +8 seperated from each other

 

I was asking this because in the Nor flash controller that i'm designing i had to tie the lower two address bits [1:0] to '0'.So i was wondering why we are doing this.

 

Thanks

 

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Xilinx Employee
Xilinx Employee
8,131 Views
Registered: ‎07-11-2011

DDRs, by their structure,  will have their density in 2 powers( 1G, 2G, 4G etc) so there should not be any issue 

Even if you would like to address last but one or last location you can very will probide that address as start address but the burst will just wrap up, please go through AR 34779 in detail,  it will explain how the addreesing works

 

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