I want to interface DDR4 with FPGA XCZU21DR using MIG ip in vivado design tool. I want to identify all pin to pin connection between FPGA and DDR4 memory. Please guide me how should I proceed.
If you want to use the soft PL MIG IP to make a memory controller in the FPGA fabric you need to review PG150 for the IP details and pinout requirements while UG583 has all the PCB layout requirements. Links to the latest versions of both of those documents are in my signature. I would also generate the IP example design in the VIvado tools to get more familiar with the IP configuration and to see what a valid DDR4 pinout looks like. The steps to generate the example design start on page 241 of PG150.
If you want to use the hardened PS memory controller then you need to look at UG1085 for the controller details starting on page 424 . UG1075 gives some examples for valid pinouts for the PS DDR4 interface on page 76. You'll also need to review UG583 for all the PCB layout and DDR4 layout requirements.
