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Observer mstrdm
Observer
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Registered: ‎08-26-2018

Interrupted burst read from RLDRAM3

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Hello,

I am trying to simulate a memory interface between Xilinx UltraScale+ Kintex FPGA (XCKU5P-FFVB676-1-E) and RLD3 memory (MT44K32M36RB-083E). I am using MIG 1.4. Data width is set to 36 bits and burst length (BL) is set to 2. Memory interface clock speed is 1066 MHz.

According to the memory datasheet/manual, the burst READ from different banks with BL2 in this memory can happen uninterrupted with one READ command satisfied per one memory clock cycle. Please see the screenshot:

manual1.PNG

I am trying to replicate this scenario, however, for some reason, the memory controller keeps interrupting READ commands every 4 clock cycles (for example, below you can see c0_rld3_cs_n signal switching off for 4 cycles after every 4 READ commands):


Capture.PNG

On the user interface side, the corresponding READ commands are applied uninterrupted, as seen below:

capture2.PNG

On the other hand, WRITE commands, when issued to the user interface in the exactly same uninterrupted way, are applied to the memory uninterrupted! Please check the screenshots:

capture4.PNGcapture3.PNG

Could you please hint on why the controller thinks it is necessary to interrupt the reads? Am I missing or misunderstanding something?

Regards,

Vladimir

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Moderator
Moderator
582 Views
Registered: ‎11-28-2016

Re: Interrupted burst read from RLDRAM3

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Hello @mstrdm,

This is most likely due to the tWTR check in the IP core (TWTR_CHECK_OFF).  If you can ensure that your traffic pattern will never violate the tWTR requirement for the part then I would turn this off and try running the simulation again.  PG150 (a link is in my signature) talks about this starting on page 528:
rld3_twtr_check.gif

 

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Moderator
Moderator
583 Views
Registered: ‎11-28-2016

Re: Interrupted burst read from RLDRAM3

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Hello @mstrdm,

This is most likely due to the tWTR check in the IP core (TWTR_CHECK_OFF).  If you can ensure that your traffic pattern will never violate the tWTR requirement for the part then I would turn this off and try running the simulation again.  PG150 (a link is in my signature) talks about this starting on page 528:
rld3_twtr_check.gif

 

Observer mstrdm
Observer
560 Views
Registered: ‎08-26-2018

Re: Interrupted burst read from RLDRAM3

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@ryana Thank you for the answer!

The issue was indeed caused by the tWTR check. I, however, have a small follow-up question.

According to the memory manual, in order to meet the tWTR requirements for my part, a single NOP command has to be issued between consecutive WRITE and READ commands:

twtr.PNG

Will turning the TWTR_CHECK off mean that the controller will not be inserting this NOP and might sometimes attempt to issue READ at the next cycle following the WRITE?

According to my simulations, even with TWTR_CHECK being off, controller always inserts 4 memory clock cycle pause between WRITE and READ:

rw.PNGrw_if.PNG

Best regards,

Vladimir

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Moderator
Moderator
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Registered: ‎11-28-2016

Re: Interrupted burst read from RLDRAM3

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Hello @mstrdm,

With tWTR off the controller won't throttle read commands like it did before with the check enabled.  It doesn't have any additional logic aside from that.  For this test case what happens if you mix the write and read commands back to back, like WR in Slot 0, RD in Slot 1, etc?

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Observer mstrdm
Observer
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Registered: ‎08-26-2018

Re: Interrupted burst read from RLDRAM3

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@ryana Thanks for the quick reply once again.

When I alternate READ and WRITE commands within the same UI clock cycle, controller, in fact, does violate the memory timing requirements:

rw3.PNGrw3_if.PNG

The PG150 document (page 514), however, already mansions that I should not attempt to share the same user_cmd cycle for both types of commands, which is acceptable.

I also tried alternating READ and WRITE between consecutive UI clock cycles. It looks like in this case, the controller always inserts four memory clock cycle delay (perhaps because it corresponds to one UI clock cycle?) when changing directions both from READ to WRITE and from WRITE to READ.

rw2.PNGrw2_if.PNG 

According to the part specifications, this even seems to be slight overkill. Do you think it would it be possible to reduce this turn-around latency without changing the controller's design significantly? Or is a single UI clock cycle the minimum delay that can be used? Removing READ throttling already helps a lot, just curious if it can be sped up further.

Have a good day!

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Moderator
Moderator
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Registered: ‎11-28-2016

Re: Interrupted burst read from RLDRAM3

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Hello @mstrdm,

Sorry for the delay in my response but yes, this gap is likely happening inside the controller core as it relates to the 1:4 core to PHY clock ratio.  Core controller functionality is frozen from the Xilinx side so no changes will be expored here and I don't recommend trying to make any manual modifications in this area as the code is fairly extensive and complicated.