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Observer
Observer
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Registered: ‎04-08-2017

Is there anyway I could probe DQS bus using ILA in MIG design example (XTP244) ??

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Hi community,

I have attached a PDF file here for detailed information.

Basically, I have two different snippets of code at the very top-level source code (i.e. example_top.v).

In Version 1, I just followed ‘inout’ pin (i.e. ddr3_dqs_p) sequentially at memory clock and delayed it by one cycle. synthesis and implementation completed successfully (Figure 1). but no DQS can be probed since none is attached to any ILA.

In Version 2, I just buffered ‘inout’ pin (i.e. ddr3_dqs_p) and delayed it by one cycle (Figure 2). synthesis completed successfully BUT implementation failed (Figures 3 and 4).

My question is: Is there anyway I could put ‘dbg_ddr3_dqs_p’ on any ILA in order to probe DQS during normal operation ?? Or at least is there anyway I can work around the implementation error as indicated in Figure 4 ?? or at least, what else should I look into ??

Thanks,

TH

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-21-2007

回复: Is there anyway I could probe DQS bus using ILA in MIG design example (XTP244) ??

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No, there's no way to use ILA to scope the 'in_dqs' and 'out_dqs' signals as it's point-point connection between the IO buffer and IO logic.

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-21-2007

回复: Is there anyway I could probe DQS bus using ILA in MIG design example (XTP244) ??

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There's no way to probe DQS signals in ILA. You have to take measurements on board. 

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Observer
Observer
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Registered: ‎04-08-2017

回复: Is there anyway I could probe DQS bus using ILA in MIG design example (XTP244) ??

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Hi kren and community,

Thanks for your previous reply. Do you know what osciliscope is the best tool for me to purchase and use if I want to consider probing DQS signals directly on the board (ZC706). Is there any add-on daughter card available as well ?? (However, my budget is limited; that's why I want to try the following question first.)

Is it possible for me to pipe 'in_dqs' and 'out_dqs' signals from the 'mig_7series_v2_4_ddr_mc_phy_wrapper.v' module all the way up to the very top-level source module (example_top.v) and declare them as 'wires' there ?? So that I could re-generate 'Memory Interface Generator (MIG 7 Series)' IP component for this design example ?? Is it possible to do that ?? All I wish to do is to attach these wires (since they are already buffered at the bottom modules) to an ILA at the very top-level module and debug these wires there. If NOT possible, I may have to consider getting an external osciloscope in order to probe these signals. 

Thanks,

TH

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-21-2007

回复: Is there anyway I could probe DQS bus using ILA in MIG design example (XTP244) ??

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No, there's no way to use ILA to scope the 'in_dqs' and 'out_dqs' signals as it's point-point connection between the IO buffer and IO logic.

View solution in original post

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