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Visitor
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Registered: ‎03-07-2018

KCU105 DDR4 calibration

I have two very similar designs (A and B) for the KCU105.  Each uses both the MIG DDR4 core and the Xilinx PCIe3 core.  The CLB LUT utilization for each is about 23% (B uses around 200 more than A).  They differ only in an area of the design which is logically remote from the DDR4 logic -- for example, there is an AXI fabric between them (though note that the MIG is configured with the standard user interface, not the AXI option).  The same constraints file is used for both designs(they also rely on the constraints internally specified within Vivado).  Both designs meet timing.

 

For A, DDR4 calibration completes successfully; for B it fails at the "write Read Sanity Check 0" stage.

 

The vivado logs are almost identical (except for obvious differences due to the differences in the design).  They do both report high congestion areas during routing, and the locations of those areas are different.  Could that be affecting the DDR4 logic routing?  The DDR4 logic is subject to physical constraints supplied internally by vivado and invisible to the user -- do they also keep other logic out, or should I add my own constraints to try to do that?

 

Or is that not what's going wrong?  Suggestions very welcome.

 

Thanks

 

joe

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Visitor
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Registered: ‎03-07-2018

To answer my own question:

 

I created a pblock surrounding where Vivado had placed the DDR4-related logic, assigned that logic to my pblock and excluded everything else.  The bitfile resulting from that passed DDR4 calibration.

 

I hesitate to mark this as "the solution", because I really don't know whether there's a better way of doing it.  If no-one weighs in over the next few days I'll come back and declare it solved.

 

joe

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Registered: ‎01-08-2019

Hello,

I have a similar issue, using Vivado 2018.3. Design A is PCIe and DDR4 MIG, and design B with also PCIe and DDR4 MIG has a 5% more logic added to the design. Both designs meet timing, the DDR4 MMCM is exactly on the same physical location in the device and all connections are identical (rst, ref clk etc). For design B I get an error during calibration: "Expected pattern was not found on GT_STATUS. Error found on Rank 0, Byte3, Nibble 7." 

For me it's not a solution to lock the IP with pblock

Any more tips? is something unstable with the FPGA device on KCU105 boards?

 

 

 

 
 
 

 

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