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Observer
Observer
1,680 Views
Registered: ‎08-24-2017

Kintex-7 MIG Address/Command/Control to Clock Length Matching

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Hi all,

 

I currently have a routed DDR3 memory design following the UG586 design guidelines. The FPGA is a XC7K160T-2FFG676I. I am using four x16 memories rated at 1866Mb/s. The interface will be operated at 1600Mb/s.

 

Per UG586, I have matched the lengths of all address/command/control signals to the DDR3 clock within 48 mil (~8ps).

 

In other design guides, I have seen the recommendation to lengthen the clock relative to the address/command/control signals:

UG583 (for Ultrascale, but still DDR3) recommends that the clock is 250 mils longer than the A/C/C midrange length.

Micron TN4108 recommends the clock be "slightly longer" longer than the A/C/C midrange length.

 

My current design does not include this extra length. Do I need to include it for the design to work? Can the 7 series MIG adjust the A/C/C signals if the clock is longer than they are?

 

Thanks.

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Xilinx Employee
Xilinx Employee
2,377 Views
Registered: ‎10-19-2015

Hi @cpeterson

 

We like to recommend CK's trace length to be greater than the address/command/control lines. However, this recommendation has the largest impact for customers running above 2133 Mb/s 

The recommendation find this helps customers increase the probability of success with DDR interfaces especially if there is any noise on the lines from cross-talk, impedance mismatches, and power fluctuations. 

 

You'll want to make sure you have delay matched the signals using the dielectric constant of your PCB material. The 48 mil constraint comes from a reference stack-up where E=4.0

 

Unfortunately, the MIG will not adjust the A/C/C. However, If the boards have already been spun and this is the only guideline you've missed, you still have a pretty good shot of a working interface at 1600Mb/s. 

 

Let me know what you think. 

-Matt 

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Teacher
Teacher
1,583 Views
Registered: ‎06-16-2013

Hi @cpeterson

 

It depends on topology of DDR3 memory.

 

If you use T-branch topology, you should accept constraint like guideline.

 

If you use fly-by topology and DRAM controller can issue write leveling and read leveling, it works fine.

 

Basically it's depend on your design.

 

I'm not sure that if MIG can issue write leveling and read leveling command, it works fine.

But I'm sure that the difference (skew) between CK and other is under 1/8 clock period (high frequency).

 

Thank you.

Best regards,

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Xilinx Employee
Xilinx Employee
2,378 Views
Registered: ‎10-19-2015

Hi @cpeterson

 

We like to recommend CK's trace length to be greater than the address/command/control lines. However, this recommendation has the largest impact for customers running above 2133 Mb/s 

The recommendation find this helps customers increase the probability of success with DDR interfaces especially if there is any noise on the lines from cross-talk, impedance mismatches, and power fluctuations. 

 

You'll want to make sure you have delay matched the signals using the dielectric constant of your PCB material. The 48 mil constraint comes from a reference stack-up where E=4.0

 

Unfortunately, the MIG will not adjust the A/C/C. However, If the boards have already been spun and this is the only guideline you've missed, you still have a pretty good shot of a working interface at 1600Mb/s. 

 

Let me know what you think. 

-Matt 

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Observer
Observer
1,531 Views
Registered: ‎08-24-2017

@mcertosi,

 

Thanks for the reply. The boards are in fab and will arrive next week. I'll keep my fingers crossed :)

 

The calculations used with my stackup did use Er = 4.0, but I assumed the differential pairs had the same propagation velocity as the single ended signals. The calculator provided by the board fab house indicated they would have the same propagation velocity.

 

Do you know if this recommendation to lengthen the clock in relation to the A/C/C signals is because the clock signal has faster propagation velocity or is it for some other reason?

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Xilinx Employee
Xilinx Employee
1,526 Views
Registered: ‎10-19-2015

Hi @cpeterson

The CK length guideline is two fold. One is to account for propagation delay differences between single ended and differential pairs. 

 

The second is to give more hold time or, allow more time for the signal to settle out after it has changed state. We've seen SI become a massive factor in the high speed designs and since our IP doesn't adjust the A/C/C lines we've decided that this is the best compromise. If you hit all the design guidelines this usually isn't a problem. I've not attributed matching CK to the rest of the bus to be the sole thing stopping an interface from calibrating. However, if your trace spacing is bad, if you don't change reference planes correctly, if you use a different trace impedance or termination resistor, all of those things will contribute to a little ringing on the ACC lines. Small variations from our guidelines with respect to issues that cause impedance mismatches will eat into the available hold time when the signals are matched to CK. 

 

Regards,

Matt 

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