08-06-2018 01:11 AM
I wanna add the 4x16bits DDR4 on my Kintex Ultrascale board.
There is a question. Whether the address/control pin should be in the middle I/O bank of interfaces that span three I/O
In 7 series, the address/control must be in the middle I/O bank of interfaces that span three I/O banks. All address/control must be in the same I/O bank. Address/control cannot be split between banks, see UG586 page 194.
But that isn't referred in KU.
08-06-2018 02:31 PM
The command/address/control pins do not need to be in the middle I/O bank of the interface. The Pin and Bank Rules section of PG150 talks about the data and address pin requirements for these interfaces starting on page 90. A link is in my signature. The big requirement here is that the command/address/control pins must all be in the same bank. I also encourage you to generate an IP example design for your project and perform your pin planning there since the tools will let you know if you violated any pin or clock requirements.