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yangtuzi3000
Visitor
Visitor
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Registered: ‎07-02-2017

LPDDR I/O Standard

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I'm working with  a LPDDR (4Mx16BitsX4Banks Mobile DDR SDRAM) on Mecrosemi FPGA,when I set it's I/O Standard is LPDDRI in Libero,LPDDR can work properly,but when I select LVCMOS18 (Lowest Power) I/O Standard,it work wrong! A small amount of data is covered by other data when read back from LPDDR.Please ask how can I solve this problem? 

LDDDR IO clock is 75M(data width is 16),and inside AXI clock is 37.5M(data width is 64)。

Thanks in advance!

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jheslip
Xilinx Employee
Xilinx Employee
1,520 Views
Registered: ‎06-30-2010

what LPDDR Interface are you doing 3 or 4? The fact that you can change the IO Standard i assume it is a PL interface and so LODDR3?

 

In UG 583 HSUL_12 is for LPDDR3 and so that is the on IOStandard that can be used, i do not believe LVCMOS18 is part of the Jedec spec. We do not support changing of the constraints / standards of the IP.

 

Page 110: https://www.xilinx.com/support/documentation/user_guides/ug571-ultrascale-selectio.pdf

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jheslip
Xilinx Employee
Xilinx Employee
1,521 Views
Registered: ‎06-30-2010

what LPDDR Interface are you doing 3 or 4? The fact that you can change the IO Standard i assume it is a PL interface and so LODDR3?

 

In UG 583 HSUL_12 is for LPDDR3 and so that is the on IOStandard that can be used, i do not believe LVCMOS18 is part of the Jedec spec. We do not support changing of the constraints / standards of the IP.

 

Page 110: https://www.xilinx.com/support/documentation/user_guides/ug571-ultrascale-selectio.pdf

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jheslip
Xilinx Employee
Xilinx Employee
1,516 Views
Registered: ‎06-30-2010
also what FPGA are you using, you mention "Mecrosemi FPGA" if so are you on the correct website?
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yangtuzi3000
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Registered: ‎07-02-2017

The problem has been solved,thanyou very much!

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