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Visitor dmtutd
Visitor
477 Views
Registered: ‎02-08-2018

LPDDR2 MIG - different "InputClkFreq" setting than GUI

I am having an issue where my build fails because of the following error:

In my design, I have a 200 MHz system clock input, which we need to use for the reference clock as well.

I set the Clock Period to 3333 ps, and when I go to the next page, it shows a valid 200 MHz (5000 ps) Input Clock Period selection. As you can see from the picture, it isn't 200.04 with decimal places as shown for other clock periods.

However, when I generate the output products and look at the mig_a.prj, it sets the InputClkFreq to 200.02 as also shown in the diagram.

Your help is greatly appreciated.

 

CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL axi4_mig_top_i/RealMemGen.lpddr2_mig_inst/u_lpddr2_mig_mig/u_iodelay_ctrl/u_idelayctrl has a clock period of 4.995 ns (frequency 200.02 Mhz) but IDELAYE2 axi4_mig_top_i/RealMemGen.lpddr2_mig_inst/u_lpddr2_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[6].iserdes_dq_.idelaye2 has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.
Resolution: Check that the IDELAYCTRL REFCLK pin is receiving a clock and that the period of the clock matches the REFCLK_FREQUENCY property of the <IDELAYE2/ODELAYE2>.

mig_a_prj.png
inputclkperiod.png
clkperiod.png
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4 Replies
Xilinx Employee
Xilinx Employee
451 Views
Registered: ‎08-21-2007

回复: LPDDR2 MIG - different "InputClkFreq" setting than GUI

You have set up the LPDDR2 controller running at 300MHz with 200MHz clock input. However, the arribute settings of the MMCM inside MIG IP have limitations. I suggest you safely ignore the warning message. 

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Moderator
Moderator
340 Views
Registered: ‎11-28-2016

回复: LPDDR2 MIG - different "InputClkFreq" setting than GUI

Hello @dmtutd ,

Using those same settings in a Kintex-7 device I generated an LPDDR2 Example Design with a 3333ps interface rate and a 200MHz System Clock with the Reference Clock set to Use System Clock and didn't generate any errors through implementation. When I wrote out the XDC file I saw the create_clock constraint was set to 4.999ps

create_clock -period 4.999 [get_ports sys_clk_p]

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Visitor dmtutd
Visitor
336 Views
Registered: ‎02-08-2018

回复: LPDDR2 MIG - different "InputClkFreq" setting than GUI

Hi @ryana,

 

I didn't get errors either, but just critical warnings. Did you not get any critical warnings?

 

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Moderator
Moderator
329 Views
Registered: ‎11-28-2016

回复: LPDDR2 MIG - different "InputClkFreq" setting than GUI

Hello @dmtutd ,

Oh, my mistake.  I did get the Critical Warnings but in this context they're safe to ignore.  If you manually modify the IP XDC to set the sys_clk period to 5ns and re-run implementation you will no longer see any CWs.

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