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dkartis2
Observer
Observer
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Registered: ‎11-07-2013

LPDDR2 with LVDS_25 Clock

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The constraints file generated from the MIG sets all of the pins, including the clock, to HSUL_12 or DIFF_HSUL_12. With inputs, the clock doesn't have to be 1.2 V, but I am unsure if a clock made for LVDS_25 would be alright. The following AR seems to suggest this functionality is alright from the FPGA's perspective. If I get this clock, then I'd set the pin to LVDS_25, but would the MIG still function?

 

AR# 43989

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vsrunga
Xilinx Employee
Xilinx Employee
15,705 Views
Registered: ‎07-11-2011

@dkartis2

 

I assume you are referrinf MIg system clock, if yes you can use LVDS_25, please refer below AR for more details

http://www.xilinx.com/support/answers/40603.html

 

Hope this helps

 

-Vanitha

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vsrunga
Xilinx Employee
Xilinx Employee
15,706 Views
Registered: ‎07-11-2011

@dkartis2

 

I assume you are referrinf MIg system clock, if yes you can use LVDS_25, please refer below AR for more details

http://www.xilinx.com/support/answers/40603.html

 

Hope this helps

 

-Vanitha

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

View solution in original post

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dkartis2
Observer
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Registered: ‎11-07-2013

Exactly what I needed, thanks

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