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jg_bds
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Registered: ‎02-01-2013

LPDDR4 routing-skew requirement deratings for a Zynq MPSoC memory interface

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We're laying-out a custom board with a Zynq+ and a Micron LPDDR4 device as the PSU memory.

Is it appropriate to use the derating tables in UG583 for straight DDR4 (Table A-3: DDR4 Data to DQS Skew Limit and Table A-4: DDR4 Address/Command/Control to CK Skew Limit), for an LPDDR4 interface?

If not, where can better derating tables be found?

Thank,

Joe G.

 

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jg_bds
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Registered: ‎02-01-2013

 

From Xilinx: "we do not derate LPDDR4 it is too tight"

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jg_bds
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Registered: ‎02-01-2013

 

From Xilinx: "we do not derate LPDDR4 it is too tight"

View solution in original post

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