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Contributor
Contributor
332 Views
Registered: ‎07-21-2020

LUTs over utilized (BRAM)

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Hello, I am trying to setup this kind of blockram. It all works just fine but I don't have enough resources to synthesis this code. This design needs too many LUTs but for me it doesn't look like it uses that much.

I get this error:

[DRC UTLZ-1] Resource utilization: Slice LUTs over-utilized in Top Level Design (This design requires more Slice LUTs cells than are available in the target device. This design requires 35788 of such cell types but only 32600 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter "drc.disableLUTOverUtilError" to 1 to change this error to warning.)

How can I solve this problem? How can I make this code more efficient?

 

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity LVDS_Blockram is
generic
(
addr_width : natural := 10;--1024x12
data_width : natural := 12
);
port
(
RST: in STD_LOGIC;
ADDR_RE : in std_logic_vector (9 downto 0);
WRITE_EN : in std_logic;
READ_EN : in std_logic;
LVDS_CLK_P : in std_logic; --125 MHz
LVDS_CLK_N : in std_logic;
CLK: in std_logic;
DIN : in std_logic_vector (11 downto 0);
DOUT : out std_logic_vector (11 downto 0);
BRAMFULL : out STD_LOGIC := '0'
);
end LVDS_Blockram;
architecture Behavioral of LVDS_Blockram is
--constant C_RAM_WIDTH : integer := 12;
--constant C_RAM_DEPTH : integer := 1024;

 


type mem_type is array ((2** addr_width) - 1 downto 0) of std_logic_vector(data_width - 1 downto 0);
signal mem : mem_type;
--signal ADDR_WR: std_logic_vector (9 downto 0) := "0000000000";
signal ADDR_WR: integer range 0 to 1023;
signal a,b: std_logic := '0';

begin
process (LVDS_CLK_P, LVDS_CLK_N)
begin
if (rising_edge(LVDS_CLK_P)) then
if(WRITE_EN = '1') then
mem((ADDR_WR))(10) <= DIN(10);
mem((ADDR_WR))(8) <= DIN(8);
mem((ADDR_WR))(6) <= DIN(6);
mem((ADDR_WR))(4) <= DIN(4);
mem((ADDR_WR))(2) <= DIN(2);
mem((ADDR_WR))(0) <= DIN(0);
elsif(READ_EN = '1') then
DOUT <= mem(conv_integer(ADDR_RE));
--elsif(WRITE_EN = '0') then
-- BRAMFULL <= '0';
--end if;
end if;
end if;
if (rising_edge(LVDS_CLK_N)) then
if(WRITE_EN = '1') then
mem((ADDR_WR))(11) <= DIN(11);
mem((ADDR_WR))(9) <= DIN(9);
mem((ADDR_WR))(7) <= DIN(7);
mem((ADDR_WR))(5) <= DIN(5);
mem((ADDR_WR))(3) <= DIN(3);
mem((ADDR_WR))(1) <= DIN(1);
ADDR_WR <= ADDR_WR + 1;
if(ADDR_WR = 1023) then
ADDR_WR <= 0;
BRAMFULL <= '1';
end if;
-- elsif(WRITE_EN = '0') then
-- DOUT <= mem(conv_integer(ADDR_RE));
end if;
end if;
end process;

end Behavioral;

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Highlighted
Teacher
Teacher
317 Views
Registered: ‎07-09-2009
Do you mean Luts or block Ram,
To use LUTS, any coding style will do,
but each bit in the RAM needs one LUT , so becomes very resource intensive.

But most ( if not all ) Xilinx FPGAs have dedicated Block Rams built into the hardware,

To infer them you need to stick strictly to the user guide template
or use the IP wizard .

Which software are you using ?
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

3 Replies
Highlighted
Teacher
Teacher
318 Views
Registered: ‎07-09-2009
Do you mean Luts or block Ram,
To use LUTS, any coding style will do,
but each bit in the RAM needs one LUT , so becomes very resource intensive.

But most ( if not all ) Xilinx FPGAs have dedicated Block Rams built into the hardware,

To infer them you need to stick strictly to the user guide template
or use the IP wizard .

Which software are you using ?
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

Highlighted
Contributor
Contributor
312 Views
Registered: ‎07-21-2020

@drjohnsmith I am using vivado. I need a BRAM with two input clocks to access different bits of the same adress. 

I will look into the templates and see if I can make it work

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Highlighted
Teacher
Teacher
242 Views
Registered: ‎07-09-2009
for referance,
block ram is also two port, with individual clocks on each port,
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>