I have a DDR-II in my board - a virtex6 family - and I want to use it in my VHDL design. When I use MIG to initialize the core I see it needs two different clock sources one named sys_clk and the other ref_clk. I have two clock sources in my board and have used one of them - let's call it main_clk - in my design before. I have just one source of clock left free for sys_clk and for ref_clk of MIG I don't have any other clcok sources on my board. I am wondering if there is a way to share sys_clk or main_clk used for the rest of my design with this one or not?
What's the frequency of your existing main_clk? Can it be used to generate a 200-MHz clock signal for the ref_clk input of the MIG? If so, you might be able to use the remaining, unused input to your chip for the MIG's sys_clk input.
Alternatively, is the frequency of main_clk suitable for use as the sys_clk input of the MIG? (You'll have to confirm that frequency option with the MIG.) Unfortunately, there are other restrictions on sys_clk that may prohibit the use of main_clk for sys_clk, even if the frequency is suitable.