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alexeytea
Participant
Participant
339 Views
Registered: ‎09-17-2018

Lowering DDR4 data rate

I have the followng setup:

  • Kintex Ultrascale+;
  • reference ddr4 clock generator: 150MHz;
  • memory part: MT40A256M16GE-083E;
  • Vivado 2018.3;
  • MIG version: 2.2.

I've configured the MIG core the following way: 

  • memory interface speed: 1200 Mhz (833ps);
  • reference input clock speed:  150.06Mhz (6664 ps).

At this setup the calibration failed at stage 15. Therefore I've tried lowering the memory speed for debug purpuses.

According to Micron dtasheet (if I understood it correctly), the -083E part's max data rate is 2400 MT/s, but it also supports lower rates, such as 1600 MT/s. So I reconfigured the core the followng way:

  • memory interface speed: 800 Mhz (1250 ps);
  • reference input clock speed:  150.00Mhz (6666 ps).

But now calibration is failng at the 1st stage. And there is my question: am I wrong thinking that memory speed could be lowered? Or I've made a mistake somewhere? (wrong Cas latency etc.)

 

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4 Replies
kren
Moderator
Moderator
329 Views
Registered: ‎08-21-2007

As the calibration failed at the 1st stage, please check the input clocking and reset according to pg150.

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alexeytea
Participant
Participant
322 Views
Registered: ‎09-17-2018

As I mentioned earlier, I've got the "working" design that fails at 15 stage. The only thing changed from there is MIG configuration (lower memory speed and reference clock).
The strange thing is that reference clock in the "working" design is slightly off (150.06 Mhz versus 150.0Mhz on the board), and in the "failng" design it is identical (150.0 Mhz).

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alexeytea
Participant
Participant
242 Views
Registered: ‎09-17-2018

I'ver received the second board and the calibration on a slower speed now fails at different stage. 

So my problem is somewhat board-specific (signal integrity).

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kshimizu
Xilinx Employee
Xilinx Employee
200 Views
Registered: ‎03-04-2018

Hello @alexeytea ,

 

How many boards have you tried? 

Do you use the CSV file?

Does the design have a only MIG example design?

 

I don’t think 150.06 is the cause at this point.

 

 

Best regards,

Kshimizu

 

Product Application Engineer Xilinx Technical Support

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