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Adventurer
Adventurer
5,083 Views
Registered: ‎12-21-2011

MCB Spartan 6 Simulation - problems with readout from ddr memory model

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Hi!

 

After many tries i finally managed to simulate MCB core with corresponding DDR 3 chip model (MT41J128M16HA-15E:D TR). 

 

I'm trying to test reading and writing modules to ensure proper behavior.

 

While reading works corectly (after comparing data at write fifo of the mcb and ddr 3 model printf statements), simulating the read process fails in my case.

 

First problem is lots of 'X' at data out bus from the MCB and on 'dq' lines in ddr interaface :

 

Snap 2012-09-24 at 14.24.48.png


Snap 2012-09-24 at 13.49.42.png

 

 

 

Second problem is even the non-X part of the read data (first 8 bits) is not identical to data i firstly wrote to the memory model 

 

Here is my testbench code for performing data-reads from ddr model :

 

  read_out_process : process
  begin  -- process read_out_process
    
    wait until finish_write = '1';

    for j in 0 to 18 loop
      
      c1_p0_cmd_instr     <= RD_COMM;
      c1_p0_cmd_bl        <= std_logic_vector(to_unsigned(63, c1_p0_cmd_bl'length));
      c1_p0_cmd_byte_addr <= std_logic_vector(to_unsigned(64 * j , c1_p0_cmd_byte_addr'length));

      wait for LCLK_PER;

      c1_p0_cmd_en <= '1';

      wait for LCLK_PER;

      c1_p0_cmd_en <= '0';

      wait until c1_p0_rd_empty = '0';

      c1_p0_rd_en <= '1';

      wait for LCLK_PER;

      for i in 0 to 63 loop
        
        data_out <= c1_p0_rd_data;
        wait for LCLK_PER;
        
      end loop;  -- i

      c1_p0_rd_en <= '0';

      wait for LCLK_PER;
      
    end loop;  -- j

    wait;

  end process read_out_process;

 

I'm using Xilinx ISE 13.4

 

Thanks for any help!

 

 

Tomek

 

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Adventurer
Adventurer
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Registered: ‎12-21-2011

Re: MCB Spartan 6 Simulation - problems with readout from ddr memory model

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i've  found solution to this problem: mcbx_dram_udm was not connected to MCB. 

 

mcbx_dram_rdm -  This output is the data mask for the upper
data byte (DQ[15:8]) when interfacing to a x16
device.

 

 

the weird things, that compliler wasn't complaining about this ...

 

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Adventurer
Adventurer
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Registered: ‎12-21-2011

Re: MCB Spartan 6 Simulation - problems with readout from ddr memory model

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i'm attaching full project file, module to simulate is m_mcb_write_controller, and it's testbench: tb_mcb_write_controller.

 

Simulation perform series of writes (1024) words and then tries to read the same data.

 

First clue is that ddr_model prints x's in the data while writing and reading occurs:

 

tb_mcb_write_controller.u_mem_c1.data_task: at time 41925002.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000007e data = xxa3

 

And those two x's at the begining of data are apparently wrong. I simulated example project and it was error free.

 

Thanks for any help 

 

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Adventurer
Adventurer
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Registered: ‎12-21-2011

Re: MCB Spartan 6 Simulation - problems with readout from ddr memory model

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i'm also attaching console output:

 

update:

 

there is one repeating error in the log file:

 

tb_mcb_write_controller.u_mem_c1.main: at time 41833752.0 ps ERROR:  tRCD violation during Write  

 

 but i couldn't find any information about what can cause it ...

 

update 2:

 

i found another clue about my problem, mcb1_dram_udm signal is always 'U', which is responsible for masking two upper bytes of the data according to UG388.pdf : 

 

Bidirectional data strobe for DQ[15:8]. This
signal is an input during Read transactions
and an output during Write transactions.

 

 

 

 

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Highlighted
Adventurer
Adventurer
6,321 Views
Registered: ‎12-21-2011

Re: MCB Spartan 6 Simulation - problems with readout from ddr memory model

Jump to solution

i've  found solution to this problem: mcbx_dram_udm was not connected to MCB. 

 

mcbx_dram_rdm -  This output is the data mask for the upper
data byte (DQ[15:8]) when interfacing to a x16
device.

 

 

the weird things, that compliler wasn't complaining about this ...

 

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