MIG 2.2 MMCM in Vivado 2018.2 unable to generate a clock frequency?

[kharobangdo]

I am using Vivado 2018.2. I am working on ZCU102 board.

I have generated DDR4 SDRAM MIG (v2.2) for the Component memory module MT40A256M16GE-075E. I have selected 625 MHz as Memory Device Interface Speed. I have selected 125 MHz as Reference Input Clock Speed as I want to use CLK_125 from ZCU102 board.

The MIG will generate an internal 625/4 clock (4:1 ratio) ie 156.25 MHz. I want the MIG MMCM to generate 2 additional clocks 156.25 & 625. ie X & 4X clock. But for some reason, this MMCM is not allowing it.

For Clock 1, I want D factor of 2 but the minimum availabe is 3. Why is that. A normal MMCM instance template gives me the ability to generate (125 * 10) / (1 * 2) = 625 MHz. But this MIG MMCM isn't allowing that. MMCM_FOUTMAX value from AC/DC switching characteristic is also 667 MHz.

So, why is MIG MMCM not being able to generate 625 MHz if my Input Reference clock is 125 MHz

[kharobangdo]

So, I implemented a small counter code on zcu102 where I use CLK_125 & pass it to an MMCM instance & generate CLK_156p25 (156.26 MHz) & CLK_625 (625 MHz) ie 1:4 ratio that I want. This MMCM was able to generate the necessary clocks so I am having a hard time imagining what could be the reason MIG MMCM is unable to do so. Xilinx fellows, please respond.