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Visitor zorjak
Visitor
11,592 Views
Registered: ‎09-08-2009

MIG 3.5 can't implement on Spartan xc6slx45

Hello, I have some problem with implementation of MIG core for Spartan xc6slx45.


I have generated the core and instanced in my desing and when I start implementation I get error durign map process saying (text below).

I have changed UCF file for MIG pins in order that this design can be used on sp605 board but I now get this error.  did anyone have this kind of problem. Also I wanted to ask this. did anyone used MIG design files for sp605. When I try to start that project it seems that some files are missing. 

I use ise ver 12.2.


Thanks for any kind of help.


Zoran

 

 

 

ERROR:Place:1333 - Following IOB's that have input/output programming are locked
   to the bank 1 that does not support such values
   IO Standard: Name = LVDS_25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR =
   BIDIR, DRIVE_STR = NR
   List of locked IOB's:
   mcb3_dram_dqs
   mcb3_dram_udqs
   mcb3_dram_dqs_n
   mcb3_dram_udqs_n
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

 

ERROR:Place:1333 - Following IOB's that have input/output programming are locked   to the bank 1 that does not support such values   IO Standard: Name = LVDS_25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR =   BIDIR, DRIVE_STR = NR   List of locked IOB's:   mcb3_dram_dqs   mcb3_dram_udqs   mcb3_dram_dqs_n   mcb3_dram_udqs_nERROR:Pack:1654 - The timing-driven placement phase encountered an error.

 


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10 Replies
Teacher eteam00
Teacher
11,587 Views
Registered: ‎07-21-2009

Re: MIG 3.5 can't implement on Spartan xc6slx45

If you are targeting DDR2 or DDR3, and not DDR 1, then VCCO for the MCB's IO BANK must not be 2.5V.  Any IOs inferred for the same IO BANK must either be moved to another bank, or re-defined to a compatible IOSTANDARD.

 

So...  what IOs do you have assigned to bank 1 which are not SSTL18 or SSTL15?  If it's the clock input instantiated by the MIG output files, then you need to manually edit your .UCF to correct the problem.

 

For example, here are a few lines from the .UCF file generated by MIG (3.61):

 

NET  "c1_sys_clk"      IOSTANDARD = LVCMOS25;
NET  "c1_sys_rst_n"    IOSTANDARD = LVCMOS18;
NET  "c1_sys_clk"      LOC = "D9" ;
NET  "c1_sys_rst_n"    LOC = "G9" ;

These represent nothing more than boilerplate assumptions made by MIG.  Just over-write them with your preference for source clock input and reset input.  You may source your MCB reset from inside the FPGA, but that's not one of the customisation options in MIG 3.61 or earlier.

 

By the way, MIG output also defaults to a 1x memory clock for the source clock.  For example, most designers do not want to provide a 333MHz clock on the circuit board connected to their FPGA.  You will also need to customise the default MIG output to instantiate (for example) a 33MHz LVCMOS33 clock input on bank 0 rather than a 333MHz LVCMOS25 clock input on bank 1 (where it will provoke the error message you listed).

 

The bottom line is that MIG does not generate final, unalterable code for your design.  You need to customise the MIG instantiation to fit your design.  Many of the simple customisations can be done from the wrapper level and out (as of MIG 3.61).  Some customisations (for example, generating multiple fabric clocks from the MCB's PLL) require editing the underlying MIG-generated source code files (down to infrastructure).

 

- Bob Elkind

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Xilinx Employee
Xilinx Employee
11,573 Views
Registered: ‎08-24-2010

Re: MIG 3.5 can't implement on Spartan xc6slx45

Hi,

 

Bob explanation is exactly what you need to follow if you wish to use MIG generated core, but here is the direct link http://www.xilinx.com/products/boards/sp605/reference_designs_12.2_archive.htm which provides you the SP605 MIG design files (SP605 MIG Design File.zip) and also the procedure on how to modify the MIG core to work on SP605 (SP605 MIG Design Creation.pdf), go through this link and download the said files for your reference.

 

--Thanks,

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Visitor zorjak
Visitor
11,548 Views
Registered: ‎09-08-2009

Re: MIG 3.5 can't implement on Spartan xc6slx45

Hello guys.

 

Thanks for your try to help but I haven't resolved problem. 

 

I mean. Before I wrote this post at first place I checked ucf file  that is generated by core generator and ucf file that is placed in project for mig example for SP605 board. 

 

I changed all my pins and pin standards and put them to be same as in ucf from example. I can say that I used the same ucf from mig example for sp605 (I just removed some pins that I won't used in my desing (led diode identificaiton)). MIG pins are configured same as in example (I compare files with total commander and they are same).

 

So I am not sure how do I get this. How people from xilinx manage to implement their desing. Besides that when I start this example mig project (that is donwloaded from http://www.xilinx.com/products/boards/sp605/reference_designs_12.2_archive.htm)  i get notification that some files are missing.

 

Nothing is clear for me really.

 

Anyway, one more time thank you for your trying to help. 

 

regards

Zoran

 

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Visitor azarfar_g
Visitor
10,719 Views
Registered: ‎03-04-2012

Re: MIG 3.5 can't implement on Spartan xc6slx45

i have your problem too.
what did you do?
really nithing is clear for me, too:(
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Voyager
Voyager
10,702 Views
Registered: ‎05-21-2008

Re: MIG 3.5 can't implement on Spartan xc6slx45

update your ISE and try again.
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Visitor sleary78
Visitor
10,685 Views
Registered: ‎03-12-2011

Re: MIG 3.5 can't implement on Spartan xc6slx45

This error looks spurious as the MCB is on bank3 and ISE seems to be trying to put it on bank 1. 

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Adventurer
Adventurer
10,594 Views
Registered: ‎02-09-2012

Re: MIG 3.5 can't implement on Spartan xc6slx45

Did you come a bit closer to that problem? I also have difficulties in instantiating a DDR3 design into a Spartan LX45 / Lx75

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Visitor przemekbary
Visitor
10,418 Views
Registered: ‎08-01-2012

Re: MIG 3.5 can't implement on Spartan xc6slx45

Hi!

Did you manage to solve your problem? This error is nagging me as well. My savvy with FPGA is rather low. 

 

Best regards

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Visitor przemekbary
Visitor
10,394 Views
Registered: ‎08-01-2012

Re: MIG 3.5 can't implement on Spartan xc6slx45

Hi!

I think I found the solution. Software calibration has to be switched off, which eliminates the need of using BIDIR buffers.

 

Best regards

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2,114 Views
Registered: ‎08-22-2014

Re: MIG 3.5 can't implement on Spartan xc6slx45



Hi everyone

Even if this topic is a bit old, I just had the same issue and I found (I think) the cause in this topic :

http://forums.xilinx.com/t5/Spartan-Family-FPGAs/LVDS-inputs-and-DDR2-DIFF-SSTL18-II-at-the-same-bank-error/td-p/165898



It seems that, in some cases, ISE disconnects the UCF file from the project, even if it does not show this separation...

This error message comes from ISE trying to place pins automatically at some random pins, and naturally, it goes wrong as random does not pick MCB dedicated pins...



It worked after removing the UCF from the project and adding it again just one sec latter.



Hope this helps
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