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Visitor
Visitor
1,190 Views
Registered: ‎09-06-2017

MIG 3.92 restriction for 8Gb DDR3 component

Hello

(ISE14.7)

I'm trying to use MIG 3.92 for creating a core for xc6slx25-2ft256 for controlling two 8Gb DDR3 component memories.

As my specific dram part number doesn't exist in suggestion list, i choose a x16 configuration base memory and try to increase the row to 16 and column to match 8Gb one but the row max range is 15 and trying to increase column to 12 gives this message:

'MIG can generate desings where the sum of Row, Column and Bank Address bits is less than or equal to 29.'

I tried with MIG 3.61 and this time, there were no problem and restriction in row address.

Can i continue with 3.61 version? can i address and use whole of 8Gb space in my design? what is the problem with 3.92 version?

 

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Xilinx Employee
Xilinx Employee
1,110 Views
Registered: ‎08-21-2007

You should go with the latest version of MIG IP in ISE 14.7. 

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