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Contributor
Contributor
8,986 Views
Registered: ‎03-07-2013

MIG 7 DDR3 support for 8Gb density components

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I need to achieve the full DDR3 addressing available in a single rank.  Thats 16 bits of row address and 11 bits of column. The usual advice to create a custom part and add row and/or column bits has failed for me (using MIG 1.9).  The DDR3 specification, JESD79-3B indicates that 8Gb DDR3 devices have a different page size (2KB versus 1KB).  The MIG behaves as if it does not know about that, and only reads/writes the lower 1KB of each 2KB page.  This cuts memory size in half and causes system malfunction.

 

DS176 says MIG2.4 supports 8 Gb density DDR3 devices, but none of the currently supported components/RDIMMs/UDIMMs/SODIMMs include any 8 Gb components.

 

I wish I could quickly edit the RTL for page size but I can not immediately locate any comment or variable that relates to that.  

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Contributor
Contributor
16,378 Views
Registered: ‎03-07-2013

Re: MIG 7 DDR3 support for 8Gb density components

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I had success generating a MIG7 DDR3 controller which drives Column bit 11 correctly, using Vivado 2014.4 and MIG version 2.3.

So there is support for the 8Gb components, as well as the largest DDR-3 SODIMMs, at 16GB, (but perhaps not when using ISE 14.5 and MIG 1.9).  In the generated RTL the page size is set by the COL_WIDTH, which is set by a parameter at the top level.

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Explorer
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Registered: ‎11-25-2014

Re: MIG 7 DDR3 support for 8Gb density components

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I'll be watching this thread closely. We want to use a 16GB Micron DDR3 SODIMM that uses 8Gb components (MT16KTF2G64HZ-1G6). The MIG has built in support for the 8GB version of this SODIMM (MT16KTF1G64HZ-1G6), so to target the 16GB version I started with the 8GB version as the base part and added the 11th column address.

 

The MIG issues no complaints about this, but there is one interesting bit of behavior. When I first create the custom part and the MIG is still open (before generating the core) the MIG correctly shows 16GB as the memory size in "Memory Details" at the bottom of the Controller Options page (first attachment). But after I generate the core, if I re-open it the MIG now shows 8GB as the memory size, even though the number of row, col, bank bits and dual rank indicate that it is 16GB (second attachment).

 

We have the 16GB SODIMM on order and will test it on the ZC706 board. We already have the 8GB part running fine. If the MIG can't address the 16GB part correctly we'll be in a world of hurt for our product plans.

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-11-2011

Re: MIG 7 DDR3 support for 8Gb density components

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@ptaddoni

 

 

You wrote :  "The MIG behaves as if it does not know about that, and only reads/writes the lower 1KB of each 2KB page.  This cuts memory size in half and causes system malfunction."

--6G should work with custom part settings provided they match the memory device on the board. Have you see this issue in simulation or hardware? Can you provide us simulation dumps that shows this behaviour ? 

 

-Vanitha 

 

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Contributor
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Registered: ‎03-07-2013

Re: MIG 7 DDR3 support for 8Gb density components

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We see the mis-behaviour in hardware using a logic analyzer to observe the DDR3 bus.  We also see the effect on stored data as each address gets written with a 50 bit incrementing pattern starting at 0.

 

I have also seen that the list of supported devices does not include any 8 Gb DDR3 components, RDIMM, UDIMM or SODIMMs they are all 4 Gb or less and so they are all having page size = 1KB. 

 

I also looked in the RTL, and I can not find any code which relates to controlling page size, which in DDR3, must be variable, because at the 8Gb density, it jumps from 1KB to 2KB.   

 

 

 

 

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Explorer
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Registered: ‎11-25-2014

Re: MIG 7 DDR3 support for 8Gb density components

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@ptaddoni -

 

It doesn't look like this question is going to get answered here. You might consider opening a service request with Xilinx:

 

http://www.xilinx.com/support/service-portal.html

 

If you decide to go that route I would appreciate it if you would post the result back to this thread. And when our 16GB SODIMM comes in I'll post back my results testing on the ZC706 board.

 

Thanks,

Bob

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Contributor
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Registered: ‎03-07-2013

Re: MIG 7 DDR3 support for 8Gb density components

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I had success generating a MIG7 DDR3 controller which drives Column bit 11 correctly, using Vivado 2014.4 and MIG version 2.3.

So there is support for the 8Gb components, as well as the largest DDR-3 SODIMMs, at 16GB, (but perhaps not when using ISE 14.5 and MIG 1.9).  In the generated RTL the page size is set by the COL_WIDTH, which is set by a parameter at the top level.

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Explorer
Explorer
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Registered: ‎11-25-2014

Re: MIG 7 DDR3 support for 8Gb density components

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@ptaddoni -

 

Thanks for posting back. Glad to hear everything is working for you.

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Contributor
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Registered: ‎03-27-2014

Re: MIG 7 DDR3 support for 8Gb density components

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@rjsefton

hi,

I am also working with 16GB memory so I wonder whether you succeed or not.
would you give me a feedback about your project?

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Contributor
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Registered: ‎03-27-2014

Re: MIG 7 DDR3 support for 8Gb density components

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@ptaddoni

 

hi, 

you mean you have succeed with zc706 board and 16GB SODIMM?

would you mind telling me which memory you have used and specific information for the custom part?

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Contributor
Contributor
6,962 Views
Registered: ‎03-07-2013

Re: MIG 7 DDR3 support for 8Gb density components

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Harding99, my board was not the eval board, and it is constrained by being wired for only one rank. Using Vivado, I am able to spin a controller that addresses an 8GB single rank SODIMM. I start with MT8KTF51264HZ-1G9 and add C11. I actually install 16GB 2-rank modules and only use one rank.  

 

My newer board is UltraScale and it is wired for two-rank SODIMMs but it seems there is still an 8GB module limitation on the MIG in DDR3 and DDR4, I wish I could exploit full 16GB DDR3 SODIMMs!   I have not looked into that issue yet.

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Visitor theo4ndzana
Visitor
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Registered: ‎08-13-2013

Re: MIG 7 DDR3 support for 8Gb density components

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Hi ptaddoni

 

I am having similar issue. Could you let me know how you "add C11" ?

 

Best Regards,

--

Theo.

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