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Visitor
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Registered: ‎08-04-2018

MIG 7 Series 2018.2 - Cannot disable data mask (dm)

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I'm trying to implement a micron DDR3 memory in a block design using the MIG on Vivado 2018.2, however, I'm unable to remove the dm[0] and dm[1] signals; this prevents me from completing the interface generation as this board uses a single x16 dram chip for it's PL connected memory (with no masking), and there are no pin locations to place the unwanted mask signals that will pass DRC in the MIG.

After reviewing related posts in the forums, it appears that there are a few checkboxes / options that are grayed and shouldn't be, the mask enable/disable being the only one that affects this particular implementation.

-Christian

Data mask checkbox is grayed, unless data width is set to 72Data mask checkbox is grayed, unless data width is set to 72

 

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Visitor
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Registered: ‎08-04-2018

回复: MIG 7 Series 2018.2 - Cannot disable data mask (dm)

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For others that may stumble across this thread, I found this limitation documented at the top of page 35 of UG586 v4.1.  As far as I can tell, the only way to access a fabric connected DDR3 (or DDR2) memory that doesn't support data mask in Vivado is to instantiate the MIG IP Core with the user interface (no AXI4) from IP Catalog in an RTL project (not in block design), uncheck the dm checkbox, roll one's own interface of choice off the user interface, then package the IP if it needs to be used in a block design.

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-21-2007

回复: MIG 7 Series 2018.2 - Cannot disable data mask (dm)

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This problem can be reproduced on my end. It is because the AXI has the byte enables which requires DM pins. So, in general it is the limitation of the core when in IP Integrator.

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Participant
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Registered: ‎02-06-2018

回复: MIG 7 Series 2018.2 - Cannot disable data mask (dm)

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That does not make sense. I can generate AXI MIG IP targetting dimms that are based on 4-bit chips, and those don't have byte enables.

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-21-2007

回复: MIG 7 Series 2018.2 - Cannot disable data mask (dm)

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Did you generate AXI MIG IP targetting dimms with/without DM enabled in block design?  I had a try but he DM check box is gray.

I mean the limiatation the DM option is invalid because the MIG IP is recalled in block design.

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Visitor
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Registered: ‎08-04-2018

回复: MIG 7 Series 2018.2 - Cannot disable data mask (dm)

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Is there a workaround (tcl etc) for the limitation in the IPI MIG instantiation?

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Visitor
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Registered: ‎08-04-2018

回复: MIG 7 Series 2018.2 - Cannot disable data mask (dm)

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Bump, any update or suggested workaround for this issue?  Thank you.

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-21-2007

回复: MIG 7 Series 2018.2 - Cannot disable data mask (dm)

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There's no workaround for this. IP is designed with DM enabled when AXI4 interface is enabled.

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Visitor
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Registered: ‎08-04-2018

回复: MIG 7 Series 2018.2 - Cannot disable data mask (dm)

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For others that may stumble across this thread, I found this limitation documented at the top of page 35 of UG586 v4.1.  As far as I can tell, the only way to access a fabric connected DDR3 (or DDR2) memory that doesn't support data mask in Vivado is to instantiate the MIG IP Core with the user interface (no AXI4) from IP Catalog in an RTL project (not in block design), uncheck the dm checkbox, roll one's own interface of choice off the user interface, then package the IP if it needs to be used in a block design.

View solution in original post

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