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Participant msauerpb
Participant
382 Views
Registered: ‎01-30-2018

MIG 7 Series and missing ports

Hi,

in our block design we use a MIG 7 Series interface to external DDR3 devices. During synthesis I will get the following warnings:

[Synth 8-5640] Port 'ui_addn_clk_2' is missing in component declaration ["X:/Vivado_V2_MultiCore_2017.4/TopLevelProject.srcs/sources_1/bd/TopLevel/synth/TopLevel.vhd":13196]
[Synth 8-5640] Port 'ui_addn_clk_3' is missing in component declaration ["X:/Vivado_V2_MultiCore_2017.4/TopLevelProject.srcs/sources_1/bd/TopLevel/synth/TopLevel.vhd":13196]
[Synth 8-5640] Port 'ui_addn_clk_4' is missing in component declaration ["X:/Vivado_V2_MultiCore_2017.4/TopLevelProject.srcs/sources_1/bd/TopLevel/synth/TopLevel.vhd":13196]
[Synth 8-5640] Port 'app_sr_active' is missing in component declaration ["X:/Vivado_V2_MultiCore_2017.4/TopLevelProject.srcs/sources_1/bd/TopLevel/synth/TopLevel.vhd":13196]
[Synth 8-5640] Port 'app_ref_ack' is missing in component declaration ["X:/Vivado_V2_MultiCore_2017.4/TopLevelProject.srcs/sources_1/bd/TopLevel/synth/TopLevel.vhd":13196]
[Synth 8-5640] Port 'app_zq_ack' is missing in component declaration ["X:/Vivado_V2_MultiCore_2017.4/TopLevelProject.srcs/sources_1/bd/TopLevel/synth/TopLevel.vhd":13196]
[Synth 8-5640] Port 'device_temp' is missing in component declaration ["X:/Vivado_V2_MultiCore_2017.4/TopLevelProject.srcs/sources_1/bd/TopLevel/synth/TopLevel.vhd":13196]

How can I avoid this warnings?

 

Unbenannt.JPG

 

In our block design we don't use these pins.

Thank your for your help.

BR

martin

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1 Reply
Moderator
Moderator
224 Views
Registered: ‎11-28-2016

Re: MIG 7 Series and missing ports

Hello @msauerpb ,

I created a quick block design in Vivado 2018.3 with a 7-Series MIG configured for DDR3 with 1 additional clock enabled while the rest were disabled and did not see any of these messages after synthesis.

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