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Observer huyongwei
Observer
398 Views
Registered: ‎04-09-2019

MIG 7 Series for Spartan-7

Hello,

      When I use my spartan-7(100fgga676),I use Mig IP core for DDR3 MT41K64M16-107,when i use Mig ip default version 4.2 (Beta verison)in vivado 2018.3, I can'nt get a init_calib_complete。but another verison vivado such as 2018.1 with mig version 4.1,I can get init_calib_complete success。so how can i use mig 4.1 with my vivado 2018.3.  I pre have a try, add mig 4.1 in vivado 2018.3 the dir(D:\Xilinx\Vivado\2018.3\data\ip\xilinx\mig_7series_v4_1) to user repository. then, i get it just like the follow picture,but when i generate the result,the vivado flash quit out。

微信截图_20190410094622.png

   please help me with my questaion!

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Xilinx Employee
Xilinx Employee
388 Views
Registered: ‎06-02-2017

回复: MIG 7 Series for Spartan-7

Hi @huyongwei 

After generating MIG IP using 2018.1, you will get all the sources of the IP in your project directory like:

<path to your project>\<your project name>.srcs\sources_1\ip\<your ip name>\<your ip name>

You can add all the necessary sources to your new project built using 2018.3.

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Xilinx Employee
Xilinx Employee
326 Views
Registered: ‎08-21-2007

回复: MIG 7 Series for Spartan-7

You can't find the init_calib_complete output after MIG IP was generated? I created a test project in 2018.3 and choose the same FPGA/DDR3 parts but the problem was no reproduced.

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