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schrepta
Observer
Observer
8,699 Views
Registered: ‎11-20-2013

MIG 7 ddr3 not getting calib_complete also have dbg_phaselock_err

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I'm using vivado 2013.3, MIG 7 ddr3 verilog IP, memory clock at 800MHz, user clock at 200 MHz, ddr data width 64 bits, ui data width 512 bits. I am performing a functional simulation, and the calib_complete never goes active.  Also the dbg_phaselock_err goes active after the dbg_phaselock_start.  I ran this simulation overnight.  All of the pll and mmcm locks are occuring. My clocks look correct. All of the resets look correct. Attached is a waveform of the memory controller module signals, for anyone to look at to see if I'm missing something. This is a non-AXI4 interface, just the simple user interface. I'v done a lot of searching and reading, and can't find a hint.  My testbench basically applies the two input clocks, reset_n, and initializes some important UI signals. Help.  Thank you.

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schrepta
Observer
Observer
14,610 Views
Registered: ‎11-20-2013

I resolved my problem.  Silly as this may sound, I forgot to instantiate the memory models in my test bench.

For my design simulation, it takes around 55us to get through the calibration (800MHz memory clock, 200MHz user clock).

View solution in original post

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vsrunga
Xilinx Employee
Xilinx Employee
8,695 Views
Registered: ‎07-11-2011

Hi,

 

>> My testbench basically applies the two input clocks, reset_n, and initializes some important UI signals

- If you are using example deisgn simulation /user design simulation sim_tb_top is the default test bench that have to be used, you may change few traffic gen parameters but the ddr3 module instantiation along with exampl_top.v/.vhd etc., have to be there as is.

 

Also infrastructure block in MIG takes care of all the clock and reset generatios, no need to derive any clock separately

 

If you are following some other approach please eloborate.

 

Also make sure that you have not changed the xdc or other settings after MIG generation if changed you have to verify your xdc through MIG verify ucf and update design option. 

 

I would suggest you to go through Simulation Flow Using Vivado Simulator and adopt the same.

If you are doing the same way and facing issues please upload mig.prj, xdc for further inputs

 

Regards,

Vanitha 

 

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schrepta
Observer
Observer
14,611 Views
Registered: ‎11-20-2013

I resolved my problem.  Silly as this may sound, I forgot to instantiate the memory models in my test bench.

For my design simulation, it takes around 55us to get through the calibration (800MHz memory clock, 200MHz user clock).

View solution in original post

0 Kudos