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Visitor duc1100
Visitor
137 Views
Registered: ‎12-16-2018

MIG 7 series DDR3 AXI slave read 50% duty cycle

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Using Vivado 2018.3 with Series 7 MiG 4.2.  Testing a MIG DDR3 IP block with the AXI slave interface on a custom board.  The measured AXI read throughput is about 50% of expected because the MiG AXI slave is only delivering data every other AXI clock cycle

My AXI master is able to accept read data every AXI clock cycle.  The AXI master holds AXI_RREADY high during the entire read transfer.  The MiG AXI slave drives AXI_RVALID high for the first two AXI clock cycles but then toggles it low every other cycle for the remainder of the AXI burst until it asserts AXI_RLAST. The expected behavoir is for the AXI slave to have data available every clock cycle and hold AXI_RVALID high the entire transfer.

These "wait states" inserted by the MIG AXI slave are captured on a logic analyzer and are causing the reduced throughput.  The wait states are not seen in the example design simulation that uses the same MiG DDR3 configuration.  In simulation the AXI slave holds AXI_RVALID high for the entire burst, i.e. no wait states.  Bursts of wait states are expected and seen during page/row misses and refresh operations but these don't explain the AXI_RVALID toggling.

MiG clock ratio is set to 4:1 with a 133.33Mhz source clock (533Mhz memory clock, 64-bit 1066 DDR3, AXI 512-bit data path).   This is a custom board but the DDR3 design is very similar to the ZC706 board that was used as a guide, i.e. same 64-bit DDR3 interface configuration just a slower memory (533Mhz vs 800Mhz).  Only deviation is the 200MHz reference clock is supplied by the MiG MMCM clock at 198.33Mhz.  The MiG interface starts up as expected and passes a custom memory test that compares data patterns written and read from memory, i.e. seems to be working just at the reduced rate. 

Ignoring page/row misses and refresh operations, what causes the AXI slave to limit the AXI burst read rate to only be every other AXI clock cycle?

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Visitor duc1100
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101 Views
Registered: ‎12-16-2018

Re: MIG 7 series DDR3 AXI slave read 50% duty cycle

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Problem fixed.

I mistakenly reduced the number of bank machines to 2 from 4.  This slipped into the build scripts during some experimentation.  When the example design was used to simulate I used the Vivado GUI with the default value of 4 so the simulation looked as expected.  After finding the configuration mistake and rerunning the simulation with the number of bank machines set to 2, the 50% RVALID duty cycle was observed.  Rebuilt the FPGA with number of banks set to 4 and got 100% RVALID duty cycle. 

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Visitor duc1100
Visitor
102 Views
Registered: ‎12-16-2018

Re: MIG 7 series DDR3 AXI slave read 50% duty cycle

Jump to solution

Problem fixed.

I mistakenly reduced the number of bank machines to 2 from 4.  This slipped into the build scripts during some experimentation.  When the example design was used to simulate I used the Vivado GUI with the default value of 4 so the simulation looked as expected.  After finding the configuration mistake and rerunning the simulation with the number of bank machines set to 2, the 50% RVALID duty cycle was observed.  Rebuilt the FPGA with number of banks set to 4 and got 100% RVALID duty cycle. 

View solution in original post

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