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Visitor kakakakaka
Visitor
358 Views
Registered: ‎05-11-2018

MIG 7 series vs old MIG (spartan 6)

Hi all,

actually I am porting a SoC from a spartan 6 with DDR2 to a virtex 7 with DDR3.

The memory IF changed and I have to wrap the signals from the old IF to the new IF.

1. The 7 series IF doesn't have a clock inputs like the old IF (pX_wr_clk, pX_rd_clk, pX_cmd_clk). But in UG586 page 168 one can see a clk signal. What clock is this?

2.The new IF has a databus width of 128 bits and I dont get how the IF is organised. My system has a databus width of 32bits. So how do I send my data to the IF?

  • should I write the 32bits to the 128 bit IF (app_wdf_data) and mask the rest out?
  • or should I wait till I have received 4x32 bits and then write them to the IF?

3. The addressbus width of the new IF is 28bits (27 downto 0). The DDR3 is organised as 16Mx16x8 banks (2Gbit,256MB) with row[13:0], bank[2:0] and column[9:0]. If I add all together I get 27bits.Where is the last bit?

I can not write 128 bits (full app_wdf_data vector, 16 bytes) x 28 bits (full app_addr vector, 2^28 addresses) to the IF, because this would lead to 4Gbits. So there is one addressbit too much. Why?

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2 Replies
Scholar jg_bds
Scholar
323 Views
Registered: ‎02-01-2013

Re: MIG 7 series vs old MIG (spartan 6)


@kakakakaka wrote:

Hi all,

actually I am porting a SoC from a spartan 6 with DDR2 to a virtex 7 with DDR3.

The memory IF changed and I have to wrap the signals from the old IF to the new IF.

1. The 7 series IF doesn't have a clock inputs like the old IF (pX_wr_clk, pX_rd_clk, pX_cmd_clk). But in UG586 page 168 one can see a clk signal. What clock is this?

That clock is the ui_clk clock signal from the MIG. You use that signal to clock all data into and out of the MIG over the User Interface.

2.The new IF has a databus width of 128 bits and I dont get how the IF is organised. My system has a databus width of 32bits. So how do I send my data to the IF?

The MIG user interface data width should be 8x the width of the DDR memory interface (for a 4:1 controller). Your memory interface ostensibly is 16 bits wide. For every user interface transaction you initiate, it results in an 8-count burst transaction between the MIG DDR controller and the DDR memory.

  • should I write the 32bits to the 128 bit IF (app_wdf_data) and mask the rest out?
  • or should I wait till I have received 4x32 bits and then write them to the IF?

You should write 128 bits as often as possible. Your SoC presumably has a processor--such as a Microblaze?  Turn on its I-Cache and D-Cache.

3. The addressbus width of the new IF is 28bits (27 downto 0). The DDR3 is organised as 16Mx16x8 banks (2Gbit,256MB) with row[13:0], bank[2:0] and column[9:0]. If I add all together I get 27bits.Where is the last bit?

The 28th address bit is a Rank address bit. It's mostly a placeholder. Since your DDR memory has only one rank, that bit will be fixed to 0.

2019-02-14_21-50-19.jpg

I can not write 128 bits (full app_wdf_data vector, 16 bytes) x 28 bits (full app_addr vector, 2^28 addresses) to the IF, because this would lead to 4Gbits. So there is one addressbit too much. Why?


-Joe G.

P.S. This might help you understand the MIG7 addressing:

https://forums.xilinx.com/t5/7-Series-FPGAs/MIG-DDR3-too-often-busy/m-p/809342

Visitor kakakakaka
Visitor
301 Views
Registered: ‎05-11-2018

Re: MIG 7 series vs old MIG (spartan 6)

Oh wow, thank you, that helped me much!

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