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Contributor
Contributor
249 Views
Registered: ‎05-11-2018

MIG 96-bit interface

The MIG tool will only allow up to a 64-bit (4x16) DDR3 Component interface to be generated.  I need to implement a 96-bit  (6x16) DDR3 component interface.  Is this at all possible?  Do I have to use two 48-bit MIGs in parallel?  Will they operate in sync with each other if driven simultaneously?  Any other ideas?

Kerry

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Xilinx Employee
Xilinx Employee
199 Views
Registered: ‎03-04-2018

Re: MIG 96-bit interface

Hello @kmwilliams ,

 

I don’t think it is possible to implement 96bits.

 

The MIG IP controller does not have synchronization pin to synchronize between two or more MIG IP controller.

The clock for MIG IP is dedicated for one MIG IP, so that the clock could not share other MIG IPs.

 

From above reasons, I don’t think it is possible.  I don’t have any ideas…

 

 

Best regards,

Kshimizu

Product Application Engineer Xilinx Technical Support

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