10-19-2020 07:47 AM - edited 10-20-2020 07:06 AM
I am having a design which is running on a custom board with part XCZU28DR-2FFVG1517E and with PL DDR4 CT4G4SFS824A.C8FF, 4gb, 2400 Mb/s SODIMM 1.2v CL17. External reference clock is set through petalinux (100MHz).
I am getting MIG Calibration error as you can see below,
What does the message "No valid data found for a given bit in the nibble when running the de-skew pattern" means? When does this happen?
Weird part is the MIG calibration is successful without any error for the same design on another custom board with the same DDR type. What could be the reason for this behavior?
I also attached the MIG core properties.
10-20-2020 06:19 AM - edited 10-20-2020 11:49 AM
An update on my debug,
I found that the error occurs Rank0, Byte1, Nibble 2, bit 1 using the report generated.
And here is the ILA debug signals from DDR4 IP core
I compared with the screenshot of debug signals from a working MIG from the Xilinx debug document, they seem the same to me but I can be wrong. I am not sure what the problem is.
10-21-2020 02:32 AM
Please compare the working the MIG pinouts are exactly the same. Are the MIG IP settings totally the same?
10-26-2020 02:40 AM