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Registered: ‎03-02-2012

MIG Calibration Issue on new batch of PCBs

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We are attempting to understand the sensitivity of the MIG (SDRAM Interface) to PCB and assembly variations for a Kintex-7 FPGA.
 

We have a board design that contains 9 Xilinx Kintex-7 FPGAs connected in a Master/Slave Arrangement. The Master (XC7K325T-2FFG900) interfaces to a Windows based PC via PCIe over cable on the upstream side and to 8 Slave (XC7K160T-2FFG676) FPGAs via high-speed serail links (Aurora) downstream. Each Slave FPGA drives 8 Dual-DACs for a total of 128 Analog channels. Each FPGA contains a 64-bit SDRAM interface (4 DDR3L SDRAMs).. The Master SDRAM interface runs at 800Mbps/400MHz, the Slave FPGAs run at the same (i.e. 800Mbps/400MHz), but we have also successfully implemented a new design which double the data rate to 1600Mbps/800MHz which we've tested on a subset of our boards.

All of the Design Guidelines contained in UG586 "Zynq-7000 SoC and 7 Series Devices Memory Interface Solutions" were followed, including close attention paid to PCB stackup, Signal Integrity (SI), trace delay matching and so on. We simulated the SI of the final PCB layout.

We've successfully assembled and tested 22 of these boards built using the same PCB fab house and assembly house over 3 build runs.  Due to assembly quality issues during the 3rd build, we determined we needed to utilize a new Assembly house, so we built 2 more boards for our 4th batch - still using the same, original PCB Fab house.
 
Both of these boards are exhibiting issues with the MIG/SDRAM interface.  Using the Debug Port signals of the MIG, we are able to determine that the MIG is failing calibration.  On one board, we re X-Rayed the SDRAMs - then had them re-flowed.  On the other board, we had the SDRAMs replaced - both with similar results.
 
Ideally, we would fix these 2 boards, but we are more concerned with moving forward on additional builds.  To that end I have a few questions:
  • How robust is the MIG interface in general - especially running at half the design data rate?
  • How sensitive is the MIG interface to PCB fab process variations - for example variations in trace impedance from PCB fab batch to batch?
  • What is sensitivity of the MIG interface to FPGA fab variations?
We are attempting to determine why the MIG is failing to ensure a high likelihood of success with our next batch of boards.  We believe we have a solid design - based on our success with first 22 boards.   We believe something in out process must have changed.  Is it the PCB fab?  The board assembly house process or the FPGAs themselves?
 
Any insight and suggestions are greatly appreciated.
 
Thank you,
 
Kevin Taberski
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Moderator
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187 Views
Registered: ‎01-09-2019

@taberski 

There are a lot of factors that can contribute to failure in the MIG and the DDR interface on your board, but I will try to answer your questions succinctly.

To your question on robustness, are you asking how easy it is to cause a failure on the DDR interface?  The answer to that question is that if you follow our PCB/all other guidance (which matches JEDEC spec.) that will provide an interface that will work under the conditions we specify via those documents.  All other conditions are pretty much impossible to say (like "what if I don't connect this termination resistor?"), besides to say that it will likely fail.  Of note, the MIG is the IP we provide, while the interface is DDR (or LPDDR or QDR, etc.).

Regarding the PCB fab process, we specify the requirements such that you should be quite clear of any slight variations in fab, but I can't say for certain without specific measurements on your interface.  This would indicate that a rule has been broken from our memory PCB guidance as the margin in that is meant to encapsulate variations in the physical board.  Basically, if you follow our guidance, and your fab doesn't cause some catastrophic failure in the build process, you should be fine.

The question for you is are you sure you don't have a marginally good board, that worked previously and now with a slight change in flow tipped it over the edge such that it is in a failing state?  Depending on your design, that is a possibility and could be worth investigating.  I will also note that we have some guidance in UG583 for Ultrascale, which has relevance for a design even in 7 series, such as the emphasis on proper ground stitching, the PCB stackup information, and Vtt termination resistor and cap. requirements.

Since you have these boards I would take proper hardware measurements of a couple of the lines of the DDR interface, the power rails, and the DDR clock.  The lines I would measure are address bit 3, a data/DQ bit, and WE.  To measure all of these, I suggest our Hardware Debug Guide which will lay out the requirements for those measurements: https://www.xilinx.com/support/answers/62181.html

Thanks,
Caleb
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Registered: ‎01-09-2019

@taberski 

There are a lot of factors that can contribute to failure in the MIG and the DDR interface on your board, but I will try to answer your questions succinctly.

To your question on robustness, are you asking how easy it is to cause a failure on the DDR interface?  The answer to that question is that if you follow our PCB/all other guidance (which matches JEDEC spec.) that will provide an interface that will work under the conditions we specify via those documents.  All other conditions are pretty much impossible to say (like "what if I don't connect this termination resistor?"), besides to say that it will likely fail.  Of note, the MIG is the IP we provide, while the interface is DDR (or LPDDR or QDR, etc.).

Regarding the PCB fab process, we specify the requirements such that you should be quite clear of any slight variations in fab, but I can't say for certain without specific measurements on your interface.  This would indicate that a rule has been broken from our memory PCB guidance as the margin in that is meant to encapsulate variations in the physical board.  Basically, if you follow our guidance, and your fab doesn't cause some catastrophic failure in the build process, you should be fine.

The question for you is are you sure you don't have a marginally good board, that worked previously and now with a slight change in flow tipped it over the edge such that it is in a failing state?  Depending on your design, that is a possibility and could be worth investigating.  I will also note that we have some guidance in UG583 for Ultrascale, which has relevance for a design even in 7 series, such as the emphasis on proper ground stitching, the PCB stackup information, and Vtt termination resistor and cap. requirements.

Since you have these boards I would take proper hardware measurements of a couple of the lines of the DDR interface, the power rails, and the DDR clock.  The lines I would measure are address bit 3, a data/DQ bit, and WE.  To measure all of these, I suggest our Hardware Debug Guide which will lay out the requirements for those measurements: https://www.xilinx.com/support/answers/62181.html

Thanks,
Caleb
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Highlighted
Visitor
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Registered: ‎03-02-2012

Caleb,

Thank you for the timely reply.  This feedback is actually quite helpful.

-Kevin

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Moderator
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Registered: ‎01-09-2019

@taberski 

If that is a sufficient answer for now, can you mark my reply as solution?

If you have more to investigate, and then want to follow up, let me know when you do get measurements and want to investigate further.

Thanks,
Caleb
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