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Scholar mistercoffee
Scholar
276 Views
Registered: ‎04-04-2014

MIG Command Path

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Hi,

 

I have a question regarding the 7 series MIG/WR interface (User Interface mode).

The seciton of UG586 on the Command Path specifies that if write data is presented after the corresponding write command then the delay between them should be less than two clock cycles.

The UG doesn't say what will happen if this isn't satisfied. Presumably the write command would be discarded by the core and need to be resent? 

The reason I ask is that I have my own traffic generator and if I want to restart it with different test parameters I need to 'flush out' the existing command queue and I am seeing unexpected results. It would be nice if a "command reset" port were included to reset the logic but not restart the 50us initialisatiojn process...

Thanks

 

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Xilinx Employee
Xilinx Employee
246 Views
Registered: ‎08-21-2007

回复: MIG Command Path

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The result is unexpect if the write data is more than two cycles later than the command. This should be avoided. There's no way to 'flush out' the existing command queue as there's fifo logic inside the controller for both data and command.

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Xilinx Employee
Xilinx Employee
247 Views
Registered: ‎08-21-2007

回复: MIG Command Path

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The result is unexpect if the write data is more than two cycles later than the command. This should be avoided. There's no way to 'flush out' the existing command queue as there's fifo logic inside the controller for both data and command.

Scholar mistercoffee
Scholar
235 Views
Registered: ‎04-04-2014

回复: MIG Command Path

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Ok, when I say flush out I really just want there to be no more read/writes to happen so that I can start afresh with a enw traffic gen sequence. If I can make sure that  I have sent the same no of commands as I have put data into thw write interface then this seems to work, but it involves being exact with the no of commands..

What I had hoped to do was just send more write commands than writes, then wait. The intention here was that those extra write commands would get ignored due to the 2 cycle limit, but they don't always seem to do. As you say, what I have seen is hard to comprehend and unexpected.

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