04-06-2018 08:22 AM
I have implemented MIG DDR2 design on Artix 7 FPGA, on a customized board. I am running the core at 250 Mhz, in 4:1 mode, with 64 bit wide read and write ports as in 4:1 mode. I am successfully able to read and write for smaller memories in my design ,let's say from addresses (27 Bits) Hex h0000 to h5000 and reading back adresses from h0000 to h4000. But the moment I increase the range of addresses let's say to h8000 or h9000, in the same design, I am getting incorrect starting and ending data. This is strange as rd_data coming from the DDR2 is valid for smaller memories in burst read and write modes, but for large memories its failing. It would be very much appreciated if someone could help me out here as to what can be the reason that its failing for large memory spaces?.
Looking forward for productive suggestions. Thanks
04-06-2018 08:30 AM
I would perform some more targeted tests to specific address ranges and check the behavior against the memory address mapping option you selected in the design. From there I would correlate the address range or address bits that are different in those accesses to see if it's related to a bank or a row switch. If possible I would use an address seeded data pattern so when you perform a write and the a read, if the read data is different, you should be able to determine if the bad read data is from a different address or corrupted all together.
I would also double check the basic things on your board like making sure the MIG is configured to match the part installed on the board and that you followed all the termination and trace length guidelines in UG586:
Start on page 196 and check that your command/address/control signals are properly terminated and your layout meets the requirements in the Trace Lengths section starting on page 198.
04-06-2018 09:05 AM
Thanks for your quick reply. Its very much appreciated.
As far as the trace length and terminations are considered, I am sure of the design as we followed the recommendations given in the UG586 manual for designing with the PCBs. I am also using an address seeded data pattern (mapping each address as data into the location and reading back). The read data is completely synchronized but when large memories of the DDR2 are used (MICRON), the starting address takes place from let's say around h0030 instead of h0000 and hence if it reads 4000 memory addresses, the ending address is also changed and added to h4030 instead of h4000. How and where should I check if it's a bank or a row switch while the memory is being accessed? Can writing to memory again after a read has any relation to this behaviour?
04-09-2018 03:36 PM
To see if a bank or row switch happens you look at the address you're driving on the app_addr and the address mapping option you selected in the MIG GUI. However based on the info you provided below it sounds like you're in trouble right from the start since you begin at address 0x0 and the data come back from address 0x30. Which such a low address that's still a column address. What I would do is make sure you're issuing a single write to address 0x0 and a single read to address 0x0 and check the returned data. Insert ILAs on these signals to do this.
Looking at your original post it sounded like things were OK if you start at 0x0 and go to 0x5000 but problems happen if you go to larger addresses. Do you mean writing and reading a large range of data, like 0x5000 transactions to any address range, or are you referring to the address range you're asserting on the app_interface? When you say larger memories do you mean putting a different memory on the board with the same MIG design? It sounds like I need more information on exactly what you're doing in order to understand what could be causing this to happen.
04-10-2018 12:55 AM
I checked with the single read and write access to address 0x00 and it worked. The problem as identified earlier is coming with only large memories beyond ranges from 0x0 to 0x5000 hex. Below this range, no matter from where I read, I am getting perfect synchronized data whether from 0x00 or from 0x100 till the ending read range value. However as soon as I increase the address space range beyond 0x5000 hex, the read values start to appear with a random offset, at times starting from 0x30 or 0x10 or 0x20 etc. I will take some snapshots with the memory values on ILA and send it to you for you to have a much better understanding.
Once again thanks for your help. Hoping to get this problem solved quickly enough.
04-10-2018 01:33 PM
If the issues start happening at address above 0x5000 then that most likely is a different row address and it's possible the upper address bits changing are coupling to some of the lower address bits. Your mapping options are either BANK_ROW_COLUMN (default) or ROW_BANK_COLUMN and if you used the default value then that address offset puts you beyond the Column range and in to the Row ranges. It's possible but unlikely the MIG configuration doesn't match the memory device on the board and that could be causing some undefined behaviors if the RAS timing (activates, precharges) when going to different rows is violated.
I would focus on and try to isolate simple write reads tests in the address range that gives you issues, isolate the address bits that are changing, and then try to measure them on the board.
04-11-2018 05:14 AM
The address mode is ROW_BANK_COLUMN. I've double checked the address ranges. Any address or data above 5000h is giving problems. I checked with chipscope the writing of the data and then reading back beyond addresses 5000h (from 5000h to 7000h) then from 4000h to 6000h and also for 0-6000 or 0-7000h. Always I am encountering issues with the higher range of addresses. Moreover for below 5000, it works perfectly fine (figure 0_5000_Success_RWR.PNG attached).
Any suggestions will be helpful.
04-11-2018 12:17 PM
It would be helpful if you had some comments with each picture that lets us know what we're looking and when we're looking at it in the sequence. Also it would be helpful to know more about your design and memory topology because I saw some duplication of signals and I wasn't sure how to treat them in this case.
Getting back to my suggestions I recommend doing a single write and a single read and capture it in a single ILA trace so you can make sure only one set of write data was issued with the write command, that the write data and write command are in sync, there were no other activities between, and then a read from that location.
04-17-2018 03:30 AM
I managed to resolve the issue by changing the timing parameters of the memory part. (trfw, tras and etc). I slightly increased the timings as given in the datasheets of the M4764M8 Micron DDR2 device and now I am able to correctly write and read on higher addresses. I used the following values for MICRON MT47H64M8-25E DDR2 memory with Artix 7 series FPGA designs:
Now I see no issues with read addresses of memories beyond 5000h or 10000h even. This only applies to 4:1 mode and I am running the core at 250 Mhz.
Thanks for your valuable input and cooperation,