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tmacqui
Observer
Observer
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Registered: ‎02-14-2019

MIG DDR3 Core and (MIG) Sys_Clk Clock Source Reuse

Hello,

I am using the MIG DDR3 Core where the system clk is being supplied by a LVDS (303MHz) differential oscillator  along with the DDR3 refrence clock LVDS (200MHz) differential oscillator. The core builds and sims fine. The interface is operated in the 4:1 mode whereby I get a 303.03/4 = 75.7575MHz clock output from the MIG to run the rest of my device with. I would like to produce another say 100MHz and 50MHz global clock but I only have those two oscillator sources on my device. Is it possible to re-use the system or reference clock by sourcing it to another MMCM or PLL to produce those additional global clocks? If so, what are your recommendations?  

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deepalir
Xilinx Employee
Xilinx Employee
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Registered: ‎02-21-2019

Hi @tmacqui

You have the following options:
1. Use the 'Additional Clock Outputs' option from MIG GUI if you are using IPI.

DDR3.PNG

 

 

 

 

 

 

 

2. The unused outputs of the MIG PLL can be used as clock outputs.  

Hope this helps. 

 

 

 

 

 

 

 

 

 

 

 

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tmacqui
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Registered: ‎02-14-2019

Hello

thanks for the quick feedback. I am using the Example_top design to check this out (PLL from the DDR3 clk_ref_p/n LVDS osc. inputs) and found that the P+R tool reported and 'unroutable solution'

I will include the example_top module so you can see how this was done. I created an PLL IP unit from the IP 'clock wizard' and I will attach the .dcp file for that instance as well.  

Here is the error message:

[Place 30-602] IO port 'clk_ref_n' is driving multiple buffers. This will lead to unplaceable/unroutable situation.
The buffers connected are:
u_mig_7series_0/u_mig_7series_0_mig/u_iodelay_ctrl/diff_clk_ref.u_ibufg_clk_ref {IBUFDS}
U_clk_ref_PLL_DDR3_lvds/inst/clkin1_ibufgds {IBUFDS}

 

Thanks, Tom

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tmacqui
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Registered: ‎02-14-2019

Hello

This message is still active. It appears that the PLL cannot be connected when using the DDR3 MIG. See the attached files indicating Vivado's response to my source files attached.

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