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Observer
Observer
297 Views
Registered: ‎07-18-2019

MIG DDR3 SDRAM testbench

Hello, I am trying to simulate traffic on the DDR3 controller of a Kintex Ultrascale, in order to estimate effective bandwith. I am using pg150 in order to understand how to handle the Traffic Generator, but Chapter 7 is not really clear to me. The product guide referes to a testbench which appear to be different to the one I was able to retreive. 

In particular, the "Testbench" section (page 256) describes the traffic generator and stimuli files, but I cannot find them anywhere. Am I reading it wrong?

Thanks in advance for the help

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-21-2007

After the DDR3 IP is generated, rigtht click on the xci file and choose "open IP example design". Then a new project-IP example design will be open. You can find the testbench in this project.

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Observer
Observer
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Registered: ‎07-18-2019

I know that, but the testbench is not the same as the one described in pg150. There is no stimuli file, therefore there is basically no way to actually customize traffic using a txt file, which is what I am looking to do

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Xilinx Employee
Xilinx Employee
202 Views
Registered: ‎08-21-2007

Do you mean the stimulus.txt file? You can find it under your project directory.

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Observer
Observer
192 Views
Registered: ‎07-18-2019

There is no stimuli.txt file in my project directory. Do you mind sharing the expected path?

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