MIG DDR3 interfaced with custom IP through AXI is too slow
I am working on a pre-existing project on VC707 board. I am trying to get data from MIG module with an AXI interface to a custom IP.
My MIG configuration is as below:
DDR3 SDRAM with CLK period = 400MHz
PHY to controller clock ratio 4:1
AXI Data width = 512, Narrow burst support enabled
Input Clock period = 200MHz
ui clock output = 100MHz
My custom IP is working at 200MHz clk generated by MIG additional clk outputs. It sends the burst trigger to MIG and receives 32bit Data x4 times which in turn is concatenated to form a 128bit data. This is the master IP and is interfaced with the AXI interconnect with a clock converter and Data width converter.
The problem I am facing is that the received data is too slow for my application. My axi_transaction_done signal is arriving at a speed of 2.5MHz. and this in turn initiates another burst. I am not getting an idea on what is posing as the bottleneck. Is this an expected speed through AXI for my configuration?
Kindly help me with some pointers on how I can improve the speed of the design. I require a data at 25Mhz speed at least.