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Observer d_pso
Observer
427 Views
Registered: ‎08-02-2013

MIG DDR3 pinout and AR# 45588

Hi,

I am trying to design a board with a Zynq 15 and some 566MHz DDR3 memory.

Applying the different rules, I arrive at the following pinout.

The MIG pin verification tool gives me an error pointing me to AR# 45588. In the AR, I read that to use the out-of-byte pins (denoted T4 in the MIG GUI), the adjacent group (T3 here) must not be a data byte and that there must be a free pin, or a VREF. So if I am not mistaken, these conditions are not violated (T3 is A0~10 and has the VREF) and therefore the tool should be happy. What did I miss here? 

NET "ddr3_addr[0]" LOC = "F1" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[1]" LOC = "G1" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[2]" LOC = "H1" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[3]" LOC = "F2" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[4]" LOC = "G2" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[5]" LOC = "E3" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[6]" LOC = "G3" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[7]" LOC = "E4" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[8]" LOC = "F4" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[9]" LOC = "G4" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[10]" LOC = "H4" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[11]" LOC = "H6" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[12]" LOC = "A4" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[13]" LOC = "C4" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[14]" LOC = "A5" | IOSTANDARD = SSTL15 ;
NET "ddr3_ba[0]" LOC = "B7" | IOSTANDARD = SSTL15 ;
NET "ddr3_ba[1]" LOC = "B8" | IOSTANDARD = SSTL15 ;
NET "ddr3_ba[2]" LOC = "C8" | IOSTANDARD = SSTL15 ;
NET "ddr3_cas_n" LOC = "B6" | IOSTANDARD = SSTL15 ;
NET "ddr3_ck_n[0]" LOC = "A6" | IOSTANDARD = DIFF_SSTL15 ;
NET "ddr3_ck_p[0]" LOC = "A7" | IOSTANDARD = DIFF_SSTL15 ;
NET "ddr3_cke[0]" LOC = "C5" | IOSTANDARD = SSTL15 ;
NET "ddr3_dm[0]" LOC = "D3" | IOSTANDARD = SSTL15 ;
NET "ddr3_dm[1]" LOC = "G8" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[0]" LOC = "B1" | IOSTANDARD = SSTL15 | IN_TERM = UNTUNED_SPLIT_40 ;
NET "ddr3_dq[1]" LOC = "C1" | IOSTANDARD = SSTL15 | IN_TERM = UNTUNED_SPLIT_40 ;
NET "ddr3_dq[2]" LOC = "D1" | IOSTANDARD = SSTL15 | IN_TERM = UNTUNED_SPLIT_40 ;
NET "ddr3_dq[3]" LOC = "B2" | IOSTANDARD = SSTL15 | IN_TERM = UNTUNED_SPLIT_40 ;
NET "ddr3_dq[4]" LOC = "D2" | IOSTANDARD = SSTL15 | IN_TERM = UNTUNED_SPLIT_40 ;
NET "ddr3_dq[5]" LOC = "E2" | IOSTANDARD = SSTL15 | IN_TERM = UNTUNED_SPLIT_40 ;
NET "ddr3_dq[6]" LOC = "B3" | IOSTANDARD = SSTL15 | IN_TERM = UNTUNED_SPLIT_40 ;
NET "ddr3_dq[7]" LOC = "C3" | IOSTANDARD = SSTL15 | IN_TERM = UNTUNED_SPLIT_40 ;
NET "ddr3_dq[8]" LOC = "E5" | IOSTANDARD = SSTL15 | IN_TERM = UNTUNED_SPLIT_40 ;
NET "ddr3_dq[9]" LOC = "F5" | IOSTANDARD = SSTL15 | IN_TERM = UNTUNED_SPLIT_40 ;
NET "ddr3_dq[10]" LOC = "D6" | IOSTANDARD = SSTL15 | IN_TERM = UNTUNED_SPLIT_40 ;
NET "ddr3_dq[11]" LOC = "G6" | IOSTANDARD = SSTL15 | IN_TERM = UNTUNED_SPLIT_40 ;
NET "ddr3_dq[12]" LOC = "D7" | IOSTANDARD = SSTL15 | IN_TERM = UNTUNED_SPLIT_40 ;
NET "ddr3_dq[13]" LOC = "E7" | IOSTANDARD = SSTL15 | IN_TERM = UNTUNED_SPLIT_40 ;
NET "ddr3_dq[14]" LOC = "F7" | IOSTANDARD = SSTL15 | IN_TERM = UNTUNED_SPLIT_40 ;
NET "ddr3_dq[15]" LOC = "G7" | IOSTANDARD = SSTL15 | IN_TERM = UNTUNED_SPLIT_40 ;
NET "ddr3_dqs_n[0]" LOC = "A1" | IOSTANDARD = DIFF_SSTL15 | IN_TERM = UNTUNED_SPLIT_40 ;
NET "ddr3_dqs_n[1]" LOC = "D8" | IOSTANDARD = DIFF_SSTL15 | IN_TERM = UNTUNED_SPLIT_40 ;
NET "ddr3_dqs_p[0]" LOC = "A2" | IOSTANDARD = DIFF_SSTL15 | IN_TERM = UNTUNED_SPLIT_40 ;
NET "ddr3_dqs_p[1]" LOC = "E8" | IOSTANDARD = DIFF_SSTL15 | IN_TERM = UNTUNED_SPLIT_40 ;
NET "ddr3_odt[0]" LOC = "D5" | IOSTANDARD = SSTL15 ;
NET "ddr3_ras_n" LOC = "C6" | IOSTANDARD = SSTL15 ;
NET "ddr3_reset_n" LOC = "B4" | IOSTANDARD = LVCMOS15 ;
NET "ddr3_we_n" LOC = "H5" | IOSTANDARD = SSTL15 ;

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3 Replies
Xilinx Employee
Xilinx Employee
390 Views
Registered: ‎08-21-2007

回复: MIG DDR3 pinout and AR# 45588

Please let me know which byte group/ bank you have placed the address and data pins?

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Observer d_pso
Observer
375 Views
Registered: ‎08-02-2013

回复: MIG DDR3 pinout and AR# 45588

Hi,

Sorry for posting to the wrong forum category.

I have some new information, if I check the "Use internal VREF" in a previous screen of the MIG GUI Wizard, the validation is sometimes OK (but I'm not allowed to run at 533MHz), I could not determine a precise sequence, but sometimes, by going back in the GUI and checking use internal VREF and then navigating back to the pinout page and loading a ucf and then validating says OK, but not always [is there possibly an uninitialized variable?]. So either the rules have changed (could you describe precisely why?) or the script is bugged (could you please send me a bugfix?).

You would have a better overview if you copy/pasted my pin assignment in a ucf file and imported it in MIG selecting a MT41J256m16XX-107 memory part. But here is a summary for you:

T0: D8~15 + UDQS/nDQS + UDM + VREF (F6 - which according toAR# 45588 is equivalent to free, but anyway, this is a DATA byte, so the other condition is not met)

T1: A12~14 + CKE + ODT + CK/nCK + nCAS + nRAS + BA0~BA2 (Address/Control byte)

T2: D0~7 + LDQS/nLDQS + LDM + nRESET (DATA byte)

T3: A0~10 + VREF (H3 - which according to AR# 45588 is equivalent to free, this is aAddress/Control byte, adjacent to T4, so this should qualify according to the AR)

T4: nWE + A11

Note that right now, I can change the pinout to anything (I'm mostly thinking about T4 where maybe some specific signals may pass the GUI check).

Also, there appears to be another bug in MIG, when you define a custom memory part, you can enter the new timings, and they seem to be used, but the new part name does not appear in the list and it is not usable elsewhere (data has to be input again in different MIG instance).

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Observer d_pso
Observer
335 Views
Registered: ‎08-02-2013

回复: MIG DDR3 pinout and AR# 45588

Hi,
Could you find what I did wrong or a bug in the MIG?
Best regards.
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