03-06-2018 05:02 PM
I have encountered an extremely frustrating problem that results in a large amount of churn from a miniscule change.
I have an instantiation of MIG (the latest included in 2017.3) and am attempting to update the ui_addn_clk_0 frequency to be 50MHz instead of 25MHz. Simple, right?
I'm able to recustomize the IP and make the change. The D (dividor) factor in the MIG reflects this. After recustomizing the IP, I am presented with the "regenerate output products" dialogue. Click generate. At this point I am _unable_ to regenerate output products for this IP because "only the parent sub-design can regenerate products for this IP" etc. etc. I _am_ able to synthesize the entire block design, though. The problem is that the ui_addn_clk_0 pin shows a property (under CONFIG) FREQ_HZ still stuck at 25MHz and not 50MHz. As a result, the erroneous 25MHz property propagates throughout the system and results in things like our UART running at the wrong baud rate.
Some things I tried out of desperation to force a "refresh" on the CONFIG of the MIG:
Finally I had to resort to the laborious process of re-adding an entire instantiation of the MIG, costing me about 20 minutes and introducing error prone work of re-wiring a handful of signals. I am continually impressed (and disappointed) with how unusable FPGA tools continue to be in this day and age. The MIG has always been a particular PITA (and I've even had an FAE tell me personally that over 80% of peoples problems arise from MIG instantiations). Absolutely ridiculous.
What is the recommended flow for updating parameters on a MIG instantiation? Why don't the properties update automatically, let alone after a full resynthesis (which should regenerate output products on it)?
03-15-2018 09:17 AM
Most parameters in IPI are not fully updated and/or propagated until the BD is validated. Are you making sure to check for the frequency change after the validation process has completed?
02-14-2019 10:20 AM
I have experienced this same issue, using Vivado 2017.4. Has there been any more progress on this issue? I have verified that the property CONFG.FREQ_HZ is NOT updated after the BD is validated. To temporarily solve my problem I added a second user clock port set to the new frequency and discontinued using the first one.
02-15-2019 12:39 PM - edited 02-15-2019 12:51 PM
This issue was reported as well in https://forums.xilinx.com/t5/Memory-Interfaces/DRC-error-with-MIG-on-Artix-7/m-p/910052/highlight/false#M13394 I filed a Change Request to investigate it further.
The workaround when re-customizing 7-Series MIG in IPI is to "Skip" the window that asks you to "regenerate MIG output products" and then Save the BD, validate the BD, save the BD and then generate the BD output products instead of just the MIG.