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Contributor
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Registered: ‎08-15-2017

MIG IP example design on vivado. is the parameter END_ADDRESS (=32'h00ffffff ) my ddr2's MAX ADDRESS?

1. I use the MIG IP example design on vivado. and I use one chip of ddr2(MT47H64M16HR-25E  bank3+row13+col10 , dq 16bits ,burst8). Then I want to test all the address of my ddr2. but I found the parameter   BEGIN_ADDRESS = 32'h00000000, parameter END_ADDRESS = 32'h00ffffff,   dose END_ADDRESS  mean the MAX ADDRESS of my ddr2?   I originally thought the MAX ADDRESS is 2^(3+13+10). They are not equal.    how to calculate the  MAX ADDRESS in app_addr?

2. what dose rank means?  parameter RANKS = 1,    dose  it mean I only use one chip of ddr2?    if I use two chip of ddr2,  RANKS = 2?

ddr.PNG

parameter code :

parameter BANK_WIDTH = 3,
// # of memory Bank Address bits.
parameter COL_WIDTH = 10,
// # of memory Column Address bits.
parameter CS_WIDTH = 1,
// # of unique CS outputs to memory.
parameter DQ_WIDTH = 16,
// # of DQ (data)
parameter DQS_WIDTH = 2,
parameter DQS_CNT_WIDTH = 1,
// = ceil(log2(DQS_WIDTH))
parameter DRAM_WIDTH = 8,
// # of DQ per DQS
parameter ECC = "OFF",
parameter ECC_TEST = "OFF",
//parameter nBANK_MACHS = 4,
parameter nBANK_MACHS = 4,
parameter RANKS = 1,
// # of Ranks.
parameter ROW_WIDTH = 13,
// # of memory Row Address bits.
parameter ADDR_WIDTH = 27,
// # = RANK_WIDTH + BANK_WIDTH
// + ROW_WIDTH + COL_WIDTH;
// Chip Select is always tied to low for
// single rank devices

//***************************************************************************
// The following parameters are mode register settings
//***************************************************************************
parameter BURST_MODE = "8",

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Moderator
Moderator
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Registered: ‎11-28-2016

Hello @retina007 ,

The value for your END_ADDRESS is just used for the traffic generator with the example design.  You can set it to a larger value as long as your don't exceed the maximum address space of your memory interface which is 26-bits.  I generated an Example Design with a larger DDR3 device and the END_ADDRESS value is the same so the behavior is as expected.

The 'Rank' value here means physical ranks of memory which are controlled by the Chip Select pins on the interface.  Typically this means you're dealing with dual die packages or you have two physical ranks of memory devices like on some UDIMMs and SODIMMs.  You can have multiple memory devices as a single rank since the command address control signals, which includes the Chip Select signals, are common for all the memory placements.  Here's an example of a block diagram showing a Micron dual rank SODIMM.
micron_dual_rank_sodimm.PNG

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Contributor
Contributor
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Registered: ‎08-15-2017

@ryana Thanks 

You mean [ADDR_WIDTH-1:0]app_addr ranges from 0 to 2^26 .  It is best to be like this.

I found END_ADDRESS in the ug586_7Series_MIS.pdf , I don't know this description.(This parameter defines the end boundary
for the port address space. The least-significant Bits[3:0] of this value are ignored. ???

ddrddr.PNG

 

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Registered: ‎11-28-2016

Hello @retina007 ,

Yes, for this configuration your maximum address space is 26-bits or 0x3FFFFFF.

The reason the lower three bits are always ignored is because the three lowest Column address bits are mapped here.  Since the controller is always running in Burst Length = 8 mode it means every single read or write transaction causes 8-bursts of data to come out of the DDR device.  This means the least significant addressable bit would be the 4th Column bit [3] while the lower three [2:0] are always ignored.

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Registered: ‎08-15-2017

@ryana 

Thanks, now I understand.

At last, They ignore The least-significant Bits[3:0] of END_ADDRESS . At our example ,we set the END_ADDRESS to 2^26 【3FFFFFF】 or 2^(26-3) 【7FFFFF】?

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Registered: ‎11-28-2016

Hello @retina007 ,

Keep the end address 2^26.

The three LS-bits are present in your address space but they are effectively ignored.

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