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Explorer
Explorer
2,052 Views
Registered: ‎07-20-2009

MIG Phy_init_done wrongly asserts

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Hi all,

I am simulating Ultra-scale design in Vivado 2015.2. I have a DDR3 memory(SODIMM) in my design. I got a DDR3 simulation model from micron and customized to my part and using in my test bench.

When I simulate, simulation showing following errors and exit. ( I am using xsim in non project mode)

 

tbTop.mem_rnk[0].gen_mem[0].u_comp_ddr3.main: at time 2605938.0 ps ERROR:   tIS violation on BA 1    by 170.0 ps 

tbTop.mem_rnk[0].gen_mem[0].u_comp_ddr3.main: at time 2605938.0 ps ERROR:   tIS violation on ADDR  3 by 170.0 ps 

etc

tbTop.mem_rnk[0].gen_mem[0].u_comp_ddr3.cmd_task: at time 4442188.0 ps ERROR: Read Failure. Initialization sequence is not complete.

 

When I checked the wave ( at MIG interface). I found phy_init_done asserted but all the data in dq and dqs are 'Z'. ( I am attaching wave here). 

Can anybody please give me a clue?

 

Regards

Anoop

 

mig_init_calib.jpg
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1 Solution

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Explorer
Explorer
3,367 Views
Registered: ‎07-20-2009

Re: MIG Phy_init_done wrongly asserts

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I found the problem solutions.

 

Problem1: init_calib_complete wrongly assert.

Reason: Unlike other FPGA families Ultra-scale bypass calibration in simulation and asset init_calib_complete. So data transactions can be seen in DQ only if it is initiated from Application side.

 

Problem2: Simulation error.

Reason: It was a connection mistake in my Tb. ddr3_cs and ddr3_cas were interchanged during the connection between MIG and DDR3 model.

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3 Replies
Explorer
Explorer
2,026 Views
Registered: ‎07-20-2009

Re: MIG Phy_init_done wrongly asserts

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Hi 

I am attaching my sample project. Just open in vivado 2015.2 and run simulation.

Can anyone from xilinx please check what is the problem?

 

Regards

Anoop

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Explorer
Explorer
1,957 Views
Registered: ‎07-20-2009

Re: MIG Phy_init_done wrongly asserts

Jump to solution

Hello all,

Really appreciate any type of help from anyone. I did not get any solution to this problem yet.

Anyone there who successfully simulated Ultra-scale MIG with ddr3 verilog model (SODIMM) with Vivado 2015.2 XSIM?

 

Regards

Anoop

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Highlighted
Explorer
Explorer
3,368 Views
Registered: ‎07-20-2009

Re: MIG Phy_init_done wrongly asserts

Jump to solution

I found the problem solutions.

 

Problem1: init_calib_complete wrongly assert.

Reason: Unlike other FPGA families Ultra-scale bypass calibration in simulation and asset init_calib_complete. So data transactions can be seen in DQ only if it is initiated from Application side.

 

Problem2: Simulation error.

Reason: It was a connection mistake in my Tb. ddr3_cs and ddr3_cas were interchanged during the connection between MIG and DDR3 model.

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