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9,671 Views
Registered: ‎04-15-2016

MIG Read and Write latency and other info required for Virtex-6 and DDR3 SODIMM RAM

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-- Master Thesis Project Abstract Description
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Create a component which makes use of external DDR3 RAM to increase the amount of data
that can be stored for the multiple Image processing modules developed by other developers.

The data throughput and speed efficiency are some major concerns.

The following data contains the background info of the resources that will be used and
the doubts that I need to clear to create an efficient component.

The project is in the stage of development in Xilinx ISE and will be tested on hardware
only if the results in simulation are satisfactory.

Current MIG related knowledge or experience is just around a month in which I have been
able to write and read the data to and from the RAM in simulation.

P.S.: I have gone through the MIG User Guide (UG406 March 20, 2013) to clear my doubts
but was not successful.
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-- Resource Info
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FPGA Family                     : Virtex 6
Device                          : XC6VLX240T
Package                         : ff1156
Speed Grade                     : -2

Development Board               : HiTech Global Virtex-6 LX240T (HTG-V6-PCIE UG)
RAM Support                     : Upto 4GB DDR3 SODIMM

Xilinx ISE Version              : 14.3
Description Language            : VHDL

MIG IP Core Version             : 3.92

Burst Length                    : BL8
Ordering                        : Strict
Frequency                       : 533.33 MHz
Time Period                     : 1875 ps
Data Width                      : 64 bits
RAM Size                        : 1GB
Memory part for simulation      : MT4JSF12864HZ-1G4

RAM Module                      : CT12864BC1067 Crucial DDR3 SODIMM Memory Module
(will be used with actual hardware)
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-- Doubts ?
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1. Will the difference in the RAM used for simulation and the physical RAM that will be used
in hardware have any effect on my code ?

Will I need to make any changes to the written code ?
(I think the code should remain same. I need your confirmation)
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2. Worst case Read latency (in memory clock cycles)?
(In MIG User Guide UG406 March 20, 2013 PG 122)
Read latency is mentioned for UI to UI interface as
    a) Read to an unopened bank    : 40 memory clock cycles
    b) Read to an opened bank      : 38 memory clock cycles
    Above values are in absence of refresh, zqcalib and periodic reads

I need to know the effect of
    a) ACTIVATE command ? (I think it is 2 memory clock cycles )
    b) PRECHARGE command ?
    c) AUTO REFRESH command ?
    d) How often does the AUTO REFRESH occur ?
    e) CAS Latency ?
    f) T_RAS and T_RCD effect ?
    g) refresh, zqcalib and periodic reads effect ?

What are the above individual values and how do they effect the above mentioned
Read latency and what will be my final worst case Read latency ?
(i.e. Time duration between the read command given and the data appearing on the read bus)
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3. Worst case Write latency (in memory clock cycles)?
(i.e. Time duration between the write command given and the data appearing in the memory)
-----------------------------------------------------------------------------------------

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4. Time after a Write command when a Read command to retrieve the same value can be issued ?
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5. Depth of the Write FIFO for the MIG ?
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6. How many burst writes can I give one after the other ?

What is the time duration (in memory clock cycles) I have to wait to issue next
burst write ?
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7. Any other latencies or MIG performance parameters that can help in designing the
system architecture ?
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With Best Regards,
Lodaya, Bhaveen.
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1 Solution

Accepted Solutions
Scholar austin
Scholar
17,962 Views
Registered: ‎02-27-2008

Re: MIG Read and Write latency and other info required for Virtex-6 and DDR3 SODIMM RAM

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Did you read:

 

http://www.xilinx.com/support/answers/36719.html

Austin Lesea
Principal Engineer
Xilinx San Jose
3 Replies
Scholar austin
Scholar
17,963 Views
Registered: ‎02-27-2008

Re: MIG Read and Write latency and other info required for Virtex-6 and DDR3 SODIMM RAM

Jump to solution

Did you read:

 

http://www.xilinx.com/support/answers/36719.html

Austin Lesea
Principal Engineer
Xilinx San Jose
9,659 Views
Registered: ‎04-15-2016

Re: MIG Read and Write latency and other info required for Virtex-6 and DDR3 SODIMM RAM

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Thanks for your reply Austin. I will go through the link and try to find out as much as I can. I would like to keep this thread open for some time till I can clear all my doubts.

 

With Best Regards,

Lodaya, Bhaveen.

With Best Regards,
Lodaya, Bhaveen.
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Highlighted
Scholar austin
Scholar
9,651 Views
Registered: ‎02-27-2008

Re: MIG Read and Write latency and other info required for Virtex-6 and DDR3 SODIMM RAM

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b,


Yes, come back and let us know if anything is missing,

Austin Lesea
Principal Engineer
Xilinx San Jose