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jbcga1986
Adventurer
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Registered: ‎11-04-2010

MIG Single Ended System Clock fails while Clocking Wizard is also present

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Hello,

 

I am working on a project where I want to incorporate a MIG Core.

I use Vivado 2014.4 and I target the KC705 development board.

The block design consists of a Microblaze and its BRAM, two Processor System Resets, a Clocking Wizard and the MIG Core.

What I would like to do is connect the clock_out_1 signal of the Clocking Wizard to the System Clock of the MIG Core.

Since the MIG Core by default is set to differential input I try to set it to single-ended.

There is a known issue, though, when trying to set the system clock to single-ended so I try to workaround this issue by following the second of the suggested solutions in the AR#42831.

Even if I do this the design fails with critical warnings.

Searching the XDC file it seems that two of the MIG signals use the AD11 and AD12 pins which are already occupied by the Clocking Wizard.

I also get warnings regarding the sys_clk_i of the MIG such as: cannot set property 'VCCAUX_IO', because the property does not exist for objects of type 'pin'. 

 

Below I provide the warnings that I get in details:

 

[Vivado 12-1411] Cannot set LOC property of ports, Terminal ddr3_sdram_we_n cannot be placed on AD12 (IOB_X1Y76) because the pad is already occupied by terminal sys_diff_clock_clk_p possibly due to user constraint ["/home/dimitrios/Vivado_Logs/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_1/design_1_mig_7series_0_1/user_design/constraints/design_1_mig_7series_0_1.xdc":534]

 

[Vivado 12-1411] Cannot set LOC property of ports, Terminal ddr3_sdram_cs_n[0] cannot be placed on AD11 (IOB_X1Y75) because the pad is already occupied by terminal sys_diff_clock_clk_n possibly due to user constraint ["/home/dimitrios/Vivado_Logs/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_1/design_1_mig_7series_0_1/user_design/constraints/design_1_mig_7series_0_1.xdc":558]

 

[Netlist 29-160] Cannot set property 'VCCAUX_IO', because the property does not exist for objects of type 'pin'. ["/home/dimitrios/Vivado_Logs/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_1/design_1_mig_7series_0_1/user_design/constraints/design_1_mig_7series_0_1.xdc":609]

 

[Netlist 29-160] Cannot set property 'IOSTANDARD', because the property does not exist for objects of type 'pin'. ["/home/dimitrios/Vivado_Logs/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_1/design_1_mig_7series_0_1/user_design/constraints/design_1_mig_7series_0_1.xdc":610]

 

[Netlist 29-160] Cannot set property 'PACKAGE_PIN', because the property does not exist for objects of type 'pin'. ["/home/dimitrios/Vivado_Logs/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_1/design_1_mig_7series_0_1/user_design/constraints/design_1_mig_7series_0_1.xdc":611]

 

I have, also, attached a zip containing the XDC file of the MIG Core, a TCL file with my block design and the XDC file with the User Constraints.

 

Is there any way to make it work?

Are there any suggestions?

 

Thank you!

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vsrunga
Xilinx Employee
Xilinx Employee
15,659 Views
Registered: ‎07-11-2011

Hi,

 

The AR is a known issue in older MIG version which is fixed in 2.3

Single ended or differential should be selected only when you drive the system clock from external pins, if you want to connect clocking wizard output to sys clock please select no_buffer option as shown below and retry.

 

no_buff.png

 

Also for other errors I suspect if the pinout has issue, as this is xilinx boaard I would suggest you to down load the pinout from Xilinx boards and kits site and just load read in MIG fixed pinout read ucf option and recheck

 

https://secure.xilinx.com/webreg/clickthrough.do?cid=370263&license=RefDesLicense&filename=xtp196-kc705-mig-c-2014-3.pdf&languageID=1

 

https://secure.xilinx.com/webreg/clickthrough.do?cid=370268&license=RefDesLicense&filename=rdf0186-kc705-mig-c-2014-3.zip&languageID=1

 

 

Hope this helps

  

-Vanitha

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4 Replies
vsrunga
Xilinx Employee
Xilinx Employee
15,660 Views
Registered: ‎07-11-2011

Hi,

 

The AR is a known issue in older MIG version which is fixed in 2.3

Single ended or differential should be selected only when you drive the system clock from external pins, if you want to connect clocking wizard output to sys clock please select no_buffer option as shown below and retry.

 

no_buff.png

 

Also for other errors I suspect if the pinout has issue, as this is xilinx boaard I would suggest you to down load the pinout from Xilinx boards and kits site and just load read in MIG fixed pinout read ucf option and recheck

 

https://secure.xilinx.com/webreg/clickthrough.do?cid=370263&license=RefDesLicense&filename=xtp196-kc705-mig-c-2014-3.pdf&languageID=1

 

https://secure.xilinx.com/webreg/clickthrough.do?cid=370268&license=RefDesLicense&filename=rdf0186-kc705-mig-c-2014-3.zip&languageID=1

 

 

Hope this helps

  

-Vanitha

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jbcga1986
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8,863 Views
Registered: ‎11-04-2010

Dear Vanitha,

 

Thank you very much for your reply!

I followed your suggestions and I no longer get the critical warnings that I got earlier!

This was the solution to my problem, needless to say it is clear to me that I am at the right approach now.

 

Nevertheless, I now get the following error: 

 

[Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_1] >

design_1_i/clk_wiz_1/inst/clkin1_ibufgds (IBUFDS.O) is locked to IOB_X1Y76
design_1_i/clk_wiz_1/inst/mmcm_adv_inst (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X1Y2

The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.

Clock Rule: rule_mmcm_bufg
Status: PASS
Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
design_1_i/clk_wiz_1/inst/mmcm_adv_inst (MMCME2_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME2_ADV_X1Y2
design_1_i/clk_wiz_1/inst/clkf_buf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0

Clock Rule: rule_mmcm_bufg
Status: PASS
Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
design_1_i/clk_wiz_1/inst/mmcm_adv_inst (MMCME2_ADV.CLKOUT0) is provisionally placed by clockplacer on MMCME2_ADV_X1Y2
and design_1_i/clk_wiz_1/inst/clkout1_buf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y1

 

I added the set_property CLOCK_DEDICATED_ROUTE BACKBONE to my XDC file as it was suggested (I also searched the forum) and I still get that error.

Any other suggestions?

 

Thank you!

 

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vsrunga
Xilinx Employee
Xilinx Employee
8,858 Views
Registered: ‎07-11-2011

Hi,

 

CLOCK Dedicated route constraint in XDC should fix the place error, I guess if it is added properly or the tool has not obeyed it.

As your original issue is resolved I would suggest to close this thread and for the new error please start a new one with your updated design so that one of us can look in to it and share our findings.

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jbcga1986
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Registered: ‎11-04-2010
Hi,

I might have not set it properly so I will try again!
If the error keeps existing I will start a new thread.
Thank you very much!
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