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Registered: ‎11-28-2011

MIG Timing (Setup) Error with Virtex 7

Getting the same timing error as the post below. It's a single setup error between the MEMREFCLK and PHYCTLMSTREMPTY.


The path seems pretty straight forward.




Running Vivado 2017.2, with the V7 690t


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Mentor jmcclusk
Registered: ‎02-24-2014

Re: MIG Timing (Setup) Error with Virtex 7

Two possibilities here, either 


A)  The two blocks are too far apart, and there is no physical path short enough to meet the setup time (unlikely).


B) You have congestion in the routing, and the router can't find a solution to meet all setup timing in that area.  (more likely)


You can determine cases A) or B) by loading the design in Vivado, then bring up that schematic in a window to show the timing failure.  Then unroute EVERYTHING.   (TCL console command: route_design -unroute )  Then route that net that failed timing before...  (TCL command:  route_design -nets [get_nets failing_net]  )   does it meet timing now?   If it does, then you have a congestion problem.    If it fails timing again, then placement is the problem.  


If congestion is your issue, then there are a couple of measures that can be implemented..  The mildest is to insert a set_max_delay -datapaths_only on the slow net, and a more strict measure is to fix the routing, using the method shown on page 154 of UG903.


If placement is the problem, then you'll have to dig into the MIG constraint file, and see if you can determine why this happened.



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Xilinx Employee
Xilinx Employee
Registered: ‎09-20-2012

Re: MIG Timing (Setup) Error with Virtex 7

Hi @polyee13


This path uses dedicated routing resources and in general does not fail timing.


I saw a similar issue in the past where the below MIG rule was not followed "MIG PLL must be in same IO bank/clock region as that of the clock sent to the memory CK". Can you confirm if the above rule is followed?


If you have followed the above guideline and still seeing the issue share IP XCI and PRJ files. Also share the post route checkpoint of failing design.



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