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whitleda
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Registered: ‎11-21-2013

MIG UltraScale C_S_AXI_CTRL_DATA_WIDTH is being set to C_S_AXI_DATA_WIDTH

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I am getting an AXI interconnect DATA_WIDTH mismatch because it appears the C_S_AXI_CTRL_DATA_WIDTH is being incorrectly set to the same width of C_S_AXI_DATA_WIDTH as seen in the attachement.

 

If C_S_AXI_CTRL_DATA_WIDTH should be 256 bit wide, then the interconnect is not detecting the width correctly.  This is MIG 6.1 in Vivado 2014.4.

MIG UltraScale.JPG
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whitleda
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Quick note on this topic...it is not possible to generate the MIG output product rtl due to the errors kicked by the incorrect width of C_S_AXI_CTRL_DATA_WIDTH.  This is regardless of the setting of C_S_AXI_DATA_WIDTH.

 

The only way I see to rid the error is to reduce the memory data width to something below 72 but this removes ECC and the C_S_AXI_CTRL interface completely so I guess this is the work around until this bug is fixed.  

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vsrunga
Xilinx Employee
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Registered: ‎07-11-2011

Hi,

 

I tried at my end but do not see the error, need your AXI Interconnect and MIG configurations, can you upload the required files and bd to help reproduce the behaviour so that we can share our findings?

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whitleda
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Please see the attached zip file for the design.  Launch the batch file to regenerate the project.

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whitleda
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From PG150:

 

"The AXI4-Lite interface is fixed at 32 data bits and signaling follows the standard AMBA AXI4-Lite specifications."

 

Appears to be a bug since the width of the C_S_AXI_CTRL_DATA_WIDTH is following the C_S_AXI_DATA_WIDTH Data width set in the MIG options shown in the attached screenshot.

DDR3 Controller Settings.jpg
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vsrunga
Xilinx Employee
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Registered: ‎07-11-2011

Hi,

 

Yes it seems to be a bug, I will file CR to get addressed, meanwhile please use either 32 bit  data width or edit the genearted RTLs following the flow outlined in AR  http://www.xilinx.com/support/answers/60323.html

 

Hope this helps

 

-Vanitha

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whitleda
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Please provide the CR # when it is available.  Thx.

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vsrunga
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Registered: ‎07-11-2011

Sure, here it is  CR# 840534 

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whitleda
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Registered: ‎11-21-2013

Quick note on this topic...it is not possible to generate the MIG output product rtl due to the errors kicked by the incorrect width of C_S_AXI_CTRL_DATA_WIDTH.  This is regardless of the setting of C_S_AXI_DATA_WIDTH.

 

The only way I see to rid the error is to reduce the memory data width to something below 72 but this removes ECC and the C_S_AXI_CTRL interface completely so I guess this is the work around until this bug is fixed.  

View solution in original post

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whitleda
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Registered: ‎11-21-2013

Can I get an update on CR# 840534?

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vsrunga
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Registered: ‎07-11-2011

CR# 840534 is fixed in 2015.1 vivado release.

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