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kriss.osmanis
Visitor
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Registered: ‎11-29-2012

MIG Write Leveling fail due to schematic (mig bank rule violation) error - routed prohibit pin to switch?

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We built custom board based on ML605 schematics (same banks, same pins for DDR3 connections)

chip: Virtex-6 LX130T-2FFG1156

MIG fails at write leveling step. (chipscope shows that dqs counter reached 1F and rises error)

 

 

It seems, that we have not followed the schematics 100%, and have routed some switches and led's to FPGA pins, that should have been left unrouted/unconnected for MIG iodelay (config prohibit). For example, pin M12 is unconnected in ML605, but we have it connected to toggle switch through a resistor.

 

We set the pin locations in .ucf as config prohibit, but there is a physical wire soldered to the pin.

 

Can this be the issue for write leveling fail?

 

We built another board based on ML605 schematics, with correct replication of DDR3 banks and the MIG works. The only difference between our two boards in schematic is the ddr3 bank pin usage.

 

 

 

 

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vsrunga
Xilinx Employee
Xilinx Employee
19,818 Views
Registered: ‎07-11-2011

Hi,

 

I mean both, for IO pins even though you connect a wire on board unless you have a VHDL + ucf you cannot use that resource

Usage is within the chip.

 

To my knowledge Xilinx has not tested the core with PROHIBIT constraint and connectivity on board so exact behaviour in this case is unknown, hence  to avoid the ambiguity suggested you to find a valid alternative to M12 and change the MIG constarints referring  "Resynchronization Clock Forwarding and Distribution Elements" section of UG406

 

 

Regards,

Vanitha

 

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vsrunga
Xilinx Employee
Xilinx Employee
12,031 Views
Registered: ‎07-11-2011

Hi,

 

Not following MIG pin rules and placement guideliness will definitely result in calibration failures.

You can check the wroking and non-working pinouts using MIG "Verify pinpout and update design" utility

Write levelling generally fails DQ to DQS trace matching guidliness were not followed.

 

Please refer UG406 for more details and if you want to debug the root cause in please visit below Master AR and follow the subsequent links

http://www.xilinx.com/support/answers/35169.html

 

Hope this helps

 

Regards,

Vanitha

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kriss.osmanis
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Registered: ‎11-29-2012

The main question are:

 

We set the pin locations in .ucf as config prohibit, but there is a physical wire soldered to the pin.

Can this be the issue for write leveling fail?

 

I know it says in the guidelines to "reserve" clock capable locations in those banks. Does "reserve" mean that pin should be left unconnected, without a trace?

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vsrunga
Xilinx Employee
Xilinx Employee
11,946 Views
Registered: ‎07-11-2011

Hi,

 

CONFIG_PROBIHIT constraint tells the tool not to use a specific resource as it has dedicated purpose somewhere else in the design.

In your case if you are using ML605 ucf as is and same clockingarchitecture, M12 is allocated for  OSERDES/OLOGIC placements hence you cannot connect it and use for other pheripherals.

 

As you can't change HW,  I think you can try to find a valid alternative to M12 and change the MIG constarints.

Please refer "Resynchronization Clock Forwarding and Distribution Elements" section of UG406 on how to do it.

 

Hope this helps

 

Regards,

Vanitha

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kriss.osmanis
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Registered: ‎11-29-2012

connect it and use for other pheripherals.


 

What do you mean by that?

Use as in FPGA chip inside (VHDL + .ucf) or use on physical pcb board (connect a wire there, etc..)?

 

 

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vsrunga
Xilinx Employee
Xilinx Employee
19,819 Views
Registered: ‎07-11-2011

Hi,

 

I mean both, for IO pins even though you connect a wire on board unless you have a VHDL + ucf you cannot use that resource

Usage is within the chip.

 

To my knowledge Xilinx has not tested the core with PROHIBIT constraint and connectivity on board so exact behaviour in this case is unknown, hence  to avoid the ambiguity suggested you to find a valid alternative to M12 and change the MIG constarints referring  "Resynchronization Clock Forwarding and Distribution Elements" section of UG406

 

 

Regards,

Vanitha

 

---------------------------------------------------------------------------------------------
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