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Explorer
Explorer
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Registered: ‎02-27-2008

MIG address space works with ISE, broken with Vivado

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I'm working on a custom Kintex 7 board with 4x MT41J512M8RA-15E:D for a total of 2GB of RAM.  I have a working ISE 14.6 Microblaze design that I'm porting to Vivado 2013.3.  In Vivado, the effective memory address space that the Microblaze sees appears to have been reduced from 2GB (0x80000000-0xFFFFFFFF) to 512MB. 

 

The MIG options between the two systems appear identical - I don't see any other place to tell MIG the memory size beyond saying I'm using MT41J512M8RA-15E's, and that the data width is 32 bits.  I've set the memory address space for the DDR to 0x80000000-0xFFFFFFFF, just like in XPS in ISE.

 

The following code:

	int *p;
	for (i = 8; i <= 0xf; i++)
	{
		p = (int*)(i << 28);
		*p = (int*)(i << 28);
	}
	for (i = 8; i <= 0xf; i++)
	{
		p = (int*)(i << 28);
		printf("%08X = %08X\r\n", p, *p);
	}

 

produces this on the ISE system:

80000000 = 80000000
90000000 = 90000000
A0000000 = A0000000
B0000000 = B0000000
C0000000 = C0000000
D0000000 = D0000000
E0000000 = E0000000
F0000000 = F0000000

 

and this on the Vivado system:

80000000 = E0000000
90000000 = F0000000
A0000000 = E0000000
B0000000 = F0000000
C0000000 = E0000000
D0000000 = F0000000
E0000000 = E0000000
F0000000 = F0000000

 Is this a bug in MIG 2.0 ver 1 for Vivado?

 

Thanks,

 

-Greg

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Explorer
Explorer
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Registered: ‎02-27-2008

Re: MIG address space works with ISE, broken with Vivado

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In my project, the mig.prj file is create by the create_bd.tcl script.  If I tweak the settings in that script and recreate the IPI block design with it, then the 2GB settings stick.  These are the values I changed:

 

C0_MEM_SIZE is now set to 2147483648 (was 536870912)

C0_S_AXI_ADDR_WIDTH is now set to 31 (was 29)

 

I'm pretty sure this is a Vivado/MIG bug, but the above changes got my code working again.

 

-Greg

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Xilinx Employee
Xilinx Employee
11,955 Views
Registered: ‎07-11-2011

Re: MIG address space works with ISE, broken with Vivado

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Hi,

 

>>In Vivado, the effective memory address space that the Microblaze sees appears to have been reduced from 2GB (0x80000000-0xFFFFFFFF) to 512MB.

 

If I am not mistaken I  assume you are using IPI and do not find suitable address space option in Microblaze corresponding to targetted memory device density in MIG, can  you please confirm ?

 

 

Regards,

Vanitha.

 

 

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Explorer
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Registered: ‎02-27-2008

Re: MIG address space works with ISE, broken with Vivado

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Correct, I'm using IP integrator.  The Microblaze + MIG are part of a block design.  The address spaces are set correctly (I think) for 2GB of DDR.  It appears that the MIG, or the auto-generated AXI interconnect to MIG, are ignoring the high address bits based on the test code I showed earlier.

 

Address Space

 

Block Diagram

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Explorer
Explorer
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Registered: ‎02-27-2008

Re: MIG address space works with ISE, broken with Vivado

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A possible clue: I just generated a new minimal project from scratch, added an IPI block design, and added MIG IP to the block design. After generating the MIG IP (same MT41J512M8RA-15E, 32 bits data width), I looked at the mig_a.prj that gets created. A few parameters in there stood out:

<C0_MEM_SIZE>536870912</C0_MEM_SIZE>
<C0_S_AXI_ADDR_WIDTH>29</C0_S_AXI_ADDR_WIDTH>

I suspect these are wrong, unless they refer to 32-bit words instead of 8-bit bytes.
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Xilinx Employee
Xilinx Employee
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Registered: ‎07-11-2011

Re: MIG address space works with ISE, broken with Vivado

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Hi,

 

In the image you posted I see 2GB, is it set manually then or you could see it by MIG configuration itself?

 

MIG_IPI_Address.png

 

Can you please show us how you configured 4x MT41J512M8RA-15E:D to get a a total of 2GB of RAM in MIG GUI ?

I guess it is taking only 1 MT41J512M8RA-15E:D

If you could attach the .BD file it would be a bit quick.

 

 

Regards,

Vanitha.

 

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Explorer
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Registered: ‎02-27-2008

Re: MIG address space works with ISE, broken with Vivado

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Hi Vanitha,

 

I did set the range manually to 2GB in the address editor, I didn't realize it should have auto-populated correctly.

 

The MT41J512M8RA-15E parts are 4 Gbits each, or 512MB, with 8 data bits.  I believe the correct way to tell MIG there are 4 of them for 2GBytes total is to set the data width to 32 (it defaults to 8 for a single part), which I did:

 

MIG Options

 

More MIG Options

 

I've attached the BD script I used to create the IPI design as well.

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Observer
Observer
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Registered: ‎07-26-2011

Re: MIG address space works with ISE, broken with Vivado

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hi all. i have exactly the same issue with my MIG. no matter what i try i cannot get it to go back to the 2GBytes. I'm using a Zynq platform with 2013.3

 

If anyone's found an answer that would be great to share.

 

i tried hacking the mig.prj and mig.xci direct, but it just resets itself back to 512Mbytes.

 

 

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Explorer
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Registered: ‎02-27-2008

Re: MIG address space works with ISE, broken with Vivado

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In my project, the mig.prj file is create by the create_bd.tcl script.  If I tweak the settings in that script and recreate the IPI block design with it, then the 2GB settings stick.  These are the values I changed:

 

C0_MEM_SIZE is now set to 2147483648 (was 536870912)

C0_S_AXI_ADDR_WIDTH is now set to 31 (was 29)

 

I'm pretty sure this is a Vivado/MIG bug, but the above changes got my code working again.

 

-Greg

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Observer
Observer
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Registered: ‎07-26-2011

Re: MIG address space works with ISE, broken with Vivado

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hi

 

i shall try that.

 

i'd be interested to see that if you had attempted to go back into the mig configuration gui whether it shows "29" again greyed out. And, that if you went all the way through to "mig-generate" that it would revert your manual overide.

 

Cheers, Russ.

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-11-2011

Re: MIG address space works with ISE, broken with Vivado

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Hi All,

 

This is reported as bug and will be fixed in future release.

Please run below command in the tcl console and see how it goes.

 

set_property modelparam_value $val [ipgui::get_modelparamspec -name $param -of $ipview]

val is value 

param is paramter name

ipview is instance name

 

 

Hope this helps.

 

 

Regards,

Vanitha.

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Registered: ‎07-26-2011

Re: MIG address space works with ISE, broken with Vivado

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alas, neither solution is working for me.

 

IDEA1)  If i overide the size in the create_bd_tcl.tcl then the MIG log file shows it being reverted.

 

IDEA2) use the set_property - vivado reports both parameters as "read-only" and will not apply my setting.

 

any other ideas?

 

For Mr Xilinx, i've attached my MIG prj file. :-)

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-11-2011

Re: MIG address space works with ISE, broken with Vivado

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Hi,

 

1 is expected,  2 is not expected, can you share the snapshot of the error and the command.

 

 

Regards,

Vanitha.

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Observer
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Re: MIG address space works with ISE, broken with Vivado

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Hi

 

when will there be a xilinx patch for this. i have several projects being upgraded to 2013.3 and i don't want to realy have to hand hack all of them...

 

Cheers,

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-11-2011

Re: MIG address space works with ISE, broken with Vivado

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Hi,

 

Yes, there is a CR on this, issue will be resolved in next version which will be released shortly, but you need to wait for a month approx.

 

Hope this helps.

 

 

Regards,

Vanitha.

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