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masavoyat
Observer
Observer
7,680 Views
Registered: ‎12-03-2014

MIG and B1760 package

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AR# 62870 indicates that B1760 package will have a single HPIO half bank which is not visible in Vivado in 2014.4.

 

What will be the features/characteristics of this half bank?

 

Can we use this halff bank for Address/control signals of a Memory Interface such as DDR3?

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vsrunga
Xilinx Employee
Xilinx Employee
13,907 Views
Registered: ‎07-11-2011

Hi,

 

MIG 2015.1 has a road map to support half banks so you will be able to use the bank for address provided it falls under PG150 pin allocation rules.

But if you have a board layout in place I would sugget to contact local FAE and he can guide you accordingly

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vsrunga
Xilinx Employee
Xilinx Employee
13,908 Views
Registered: ‎07-11-2011

Hi,

 

MIG 2015.1 has a road map to support half banks so you will be able to use the bank for address provided it falls under PG150 pin allocation rules.

But if you have a board layout in place I would sugget to contact local FAE and he can guide you accordingly

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

View solution in original post

0 Kudos