cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Explorer
Explorer
4,333 Views
Registered: ‎04-19-2016

MIG and QDRII+ SRAM interface in Zynq 7000

Jump to solution

Hello @coryb

 

I am planning to use one of Cypress QDRII+ parts in my custom design board, with Zynq 7000 XC7Z100. Could you please reply the following questions ; 

 

  • Does MIG ( Memory Interface Generator) support only DDR3 and DDR2 SDRAM interface ? Because only seen DDR3 and DDR2 SDRAM formally in MIG configuration gui independent of one of the parts is selected as Kintex, Virtex, Zynq and Ultrascale. 
  • We could not see any QDR SRAM options in MIG. So should we create custom parts in MIG IP to use QDRII+ in our designs?
  • Did you mean that, in order to match our QDR SRAM timing requirements in datasheet with MIG IP,  should we modify the internal RTL design ( pure HDL or Verilog) of MIG IP ?
  • And when we want to use QDRII+ SRAM in our design with MIG, parameters that is showed in the Table 2-12 in the section Customizing the Core of UG586 for QDRII+ is enough for us?
  • Will you plan to add the Cypress QDR SRAM part numbers directly to the later versions of MIG IP ?     

 

Thank you very much and Best Regards,

Tags (4)
0 Kudos
1 Solution

Accepted Solutions
Moderator
Moderator
7,382 Views
Registered: ‎02-11-2014

Re: MIG and QDRII+ SRAM interface in Zynq 7000

Jump to solution

Q1: Does MIG ( Memory Interface Generator) support only DDR3 and DDR2 SDRAM interface ? Because only seen DDR3 and DDR2 SDRAM formally in MIG configuration gui independent of one of the parts is selected as Kintex, Virtex, Zynq and Ultrascale.
A1: If you want to use QDRII+ components, then you need to use MIG outside of IPI and make sure AXI INTF is disabled. IPI requires the use of AXI INTF. When AXI INTF is enabled you can only use DDR2/3. We have a note on the first page of MIG that talks about this limitation.

 

Q2: We could not see any QDR SRAM options in MIG. So should we create custom parts in MIG IP to use QDRII+ in our designs?
A2: Refer to A1.

 

Q3: Did you mean that, in order to match our QDR SRAM timing requirements in datasheet with MIG IP, should we modify the internal RTL design ( pure HDL or Verilog) of MIG IP ?
A3: MIG should be generating the timing parameters correctly for you with Native Parts. If you create a custom part, you might need to modify RTL to get everything per spec.

 

Q4: And when we want to use QDRII+ SRAM in our design with MIG, parameters that is showed in the Table 2-12 in the section Customizing the Core of UG586 for QDRII+ is enough for us?
A4: Yes

 

Q5: Will you plan to add the Cypress QDR SRAM part numbers directly to the later versions of MIG IP ?
A5: Refer to A1. They are already supported.

 

Thanks,

Cory Bevins

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

5 Replies
Moderator
Moderator
7,383 Views
Registered: ‎02-11-2014

Re: MIG and QDRII+ SRAM interface in Zynq 7000

Jump to solution

Q1: Does MIG ( Memory Interface Generator) support only DDR3 and DDR2 SDRAM interface ? Because only seen DDR3 and DDR2 SDRAM formally in MIG configuration gui independent of one of the parts is selected as Kintex, Virtex, Zynq and Ultrascale.
A1: If you want to use QDRII+ components, then you need to use MIG outside of IPI and make sure AXI INTF is disabled. IPI requires the use of AXI INTF. When AXI INTF is enabled you can only use DDR2/3. We have a note on the first page of MIG that talks about this limitation.

 

Q2: We could not see any QDR SRAM options in MIG. So should we create custom parts in MIG IP to use QDRII+ in our designs?
A2: Refer to A1.

 

Q3: Did you mean that, in order to match our QDR SRAM timing requirements in datasheet with MIG IP, should we modify the internal RTL design ( pure HDL or Verilog) of MIG IP ?
A3: MIG should be generating the timing parameters correctly for you with Native Parts. If you create a custom part, you might need to modify RTL to get everything per spec.

 

Q4: And when we want to use QDRII+ SRAM in our design with MIG, parameters that is showed in the Table 2-12 in the section Customizing the Core of UG586 for QDRII+ is enough for us?
A4: Yes

 

Q5: Will you plan to add the Cypress QDR SRAM part numbers directly to the later versions of MIG IP ?
A5: Refer to A1. They are already supported.

 

Thanks,

Cory Bevins

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

Highlighted
Explorer
Explorer
4,276 Views
Registered: ‎04-19-2016

Re: MIG and QDRII+ SRAM interface in Zynq 7000

Jump to solution

Hello @coryb

 

Firstly Thank you for replies. You can see a few one more below :

 

  • What did you mean that using MIG outside of IP Integrator ( IPI)  ? You mean manually adding the MIG IP in top level hdl source file ? Or another adding method ? But I want to use MIG IP configuration GUI to make some configurations easily and fastly.
  • When I have added MIG IP from IP integrator into my design, AXI4 Interface option comes out automatically enabled and passive ( That could not be disabled).
  • You said that AXI Interface is disabled when we want to use MIG with QDR SRAM option, ok, how could we connect MIG to Zynq PS side if there is no AXI Interface  in QDR SRAM option?
  • When we enabled the QDRII+ options, will Cypress QDRII+ part number CY7C2663KV18-550BZI be seen in MIG or should we create it as custom part?

 

Thank you so much,

@doner_t

Tags (4)
0 Kudos
Highlighted
Moderator
Moderator
4,261 Views
Registered: ‎02-11-2014

Re: MIG and QDRII+ SRAM interface in Zynq 7000

Jump to solution

Hey @doner_t

 

Q1)What did you mean that using MIG outside of IP Integrator ( IPI) ? You mean manually adding the MIG IP in top level hdl source file ? Or another adding method ? But I want to use MIG IP configuration GUI to make some configurations easily and fastly.
A1)I mean adding the IP to your design via IP Catalog instead of within a Block Design or IP Integrator. You cannot use QDR in IPI in 7 series/ US or US+ as we don't have AXI Support for QDR.

 

Q2)When I have added MIG IP from IP integrator into my design, AXI4 Interface option comes out automatically enabled and passive ( That could not be disabled).
A2) This is correct. You are required to use the AXI INTF when in IPI for MIG. We have no way of disabling this.

 

Q3)You said that AXI Interface is disabled when we want to use MIG with QDR SRAM option, ok, how could we connect MIG to Zynq PS side if there is no AXI Interface in QDR SRAM option?
A3) We don't have examples of the Zynq PS interfacing with the MIG PL for QDR unfortunately. There is no planned support for AXI INTF in either MIG 7-Series or MIG UltraScale/UltraScale+. QDR is a low latency memory interface so adding an AXI Shim on top will increase the latency by an undesired amount for the majority of customers. Most customer systems cannot handle this additional latency...

 

Q4)When we enabled the QDRII+ options, will Cypress QDRII+ part number CY7C2663KV18-550BZI be seen in MIG or should we create it as custom part?
A4)Yes the CY7C2663KV18-550BZI is avilable natively in 2017.2 7-series MIG.

 

Thanks,

Cory Bevins

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Highlighted
Explorer
Explorer
4,231 Views
Registered: ‎04-19-2016

Re: MIG and QDRII+ SRAM interface in Zynq 7000

Jump to solution

Hello @coryb,

 

Thank you for your replies. 

 

  • As you offer, I have used IP Catalog to Customize MIG IP. QDRII+ SRAM option is seen now. Thank you. I have found my desired part number in MIG and made some configurations.
  • So, now, could not we insert the QDRII+ configured MIG IP ( mig_7series_0.xci as seen in the photo below ) in the block design.  design_1.bd. ( Because of AXI interface is not supoorted by QDRII+ configured MIG)  ?
  • So this means that I can not use any VDMA or DMA to write & read to/from QDRII+ configured MIG, right ?  

Thank you so much.

 

 

 

Tags (4)
mig_zynq.JPG
0 Kudos
Highlighted
Moderator
Moderator
4,224 Views
Registered: ‎02-11-2014

Re: MIG and QDRII+ SRAM interface in Zynq 7000

Jump to solution

Hey @doner_t


Q1) So, now, could not we insert the QDRII+ configured MIG IP ( mig_7series_0.xci as seen in the photo below ) in the block design. design_1.bd. ( Because of AXI interface is not supoorted by QDRII+ configured MIG) ?
A1) Yes this is possible in a way. Make sure your BD is setup exactly how you want it (all the ports you want to use with MIG are external from the BD) then create a BD wrapper (make sure to specify "Copy generated wrapper to allow user edits" instead of "Let Vivado manage wrapper and auto-update") and then you can instantiate your MIG core in the BD wrapper and connect things together.

 

Q2) So this means that I can not use any VDMA or DMA to write & read to/from QDRII+ configured MIG, right ?
A2) It is up to you as to what you want to use to interface with MIG.

 

Thanks,

Cory Bevins

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos