07-26-2016 08:11 AM
I'm having this weird issue with my MIG where subsequent addresses in a burst have incorrect column addresses. It goes from 0x008 to 0x010 to 0x018 to 0x420. That last request is really off so I'm wondering why it would do that.
Also, for some reason each burst comment on the AXI bus causes groups of 4 transfers on the DDR as is pictured. Why doesn't it do all of the burst all at once?
07-26-2016 12:10 PM
During a CAS access A10, the 0x400 part of the address in question, is used to control precharging. The Column address are limited to 0x000-0x2FF by the nature of DDR3/DDR4 memory.
Your screen shot is too small to read easily to understand the question about the burst but is your question is why does an AXI burst of 4 turn into 4 separate memory transactions? If so that is because the memory has a fixed burst size of 8 and that burst is accounted for the width change between the AXI and actual DDR memory. That is also the reason for the separation between the commands, the data needs time to burst out out.
07-26-2016 01:49 PM
Thank you, that makes a lot of sense! So that answers one question, but the next question is why would the MIG precharge after every burst? The AXI command for these transactions is a read from address 0x0001800 with ARLEN of 0x32, ARSIZE of 0x4 which SHOULD be within a single row if I'm not mistaken. But then if that's the case, why does the memory precharge after every 4th read? The column addresses on the DDR lines go like 0x00, 0x08, 0x10, 0x18(precharge)...long wait...0x20, 0x28, 0x30, 0x38(precharge)... etc etc all of them on row 0x6, bank 0x0. Makes no sense....
07-26-2016 03:44 PM
There are a number of controller options that could effect it deciding to precharge at the end of a command or not. Address mapping, and buffering/lookahead for one.
But there is also the activity with CAS_N, RAS_N, and WE_N going to X and then what looks like half low. I havent used the AXI controller but are you waiting for the initialization to complete? All three control signals being low is a mode register write.
07-26-2016 04:02 PM
Yes, I see what you're talking about. I'm not sure why all of those signals go to X (undefined) after the bursts.
As for buffering/lookahead, I did not see any options in the MIG to set that. As for address mapping, it is bank, row, col from MSB to LSB with 1 "always zero" bit at the end because of the 16-bit datawidth.
Yes, initialization is fully completed before any accesses are performed.
07-26-2016 07:16 PM
I don't have any suggestion about your questions.
But I can mention to you about some TIPS for debugging DRAM via simulation.
If you use Micron's DRAM verilog model (like ddr3.sv) for RTL simulation, I recommend to turn on DEBUG option.
When you turn on DEBUG option (ex. add "+define+OPTION" option for ncverilog), you can see debug information from Micron's DRAM simulation model in your simulation log file and STDOUT.
I'm sure that this information is very helpful for your debugging.
09-01-2016 08:22 PM
I encounter a problem.
When I issue app_addr = 0x0000, 0x0008, 0x0010, 0x0018, 0x0020, 0x0028, 0x0030, 0x0038
but the row/col address became
the row address = 0x0000, 0x0000, 0x0000, 0x0000, 0x0001, 0x0001, 0x0001, 0x0001
the column address = 0x1000, 0x1008, 0x1010, 0x1018, 0x1000, 0x1008, 0x1010, 0x1018
Can anyone help to give any suggestion?
PS. I have set ORDERING parameter "STRICT" but the results are the same.