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pgigliotti_usac
Explorer
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Registered: ‎10-22-2020

MIG design error - DRC-PDRC-34

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I have greaeted a design with a 100 mhz clock going to a clock wizard which generates a 200 and 333 Mhz clocks which I then run to the MIG core.  I have set it up with a 333 mHZ clock with 4:1 option.  Furtnermore on the memory page, it allows me to select 400 MHZ (I have also tried with it also set to 333 Mhz) but get the following warning.  It mentiones running "update timing" but am unsure on how to do that.  It certainly looks like the core is not being generated correctly.

  1. [DRC PDRC-34] MMCM_adv_ClkFrequency_div_no_dclk: The computed value 555.555 MHz (CLKIN1_PERIOD, net pll_clk3) for the VCO operating frequency of the MMCME2_ADV site MMCME2_ADV_X1Y2 (cell u_DDR3_ctrl/u_DDR3_ctrl_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i) falls outside the operating range of the MMCM VCO frequency for this device (600.000 - 1440.000 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please run update_timing to update the MMCM settings. If that does not work, adjust either the input period CLKINx_PERIOD (14.400002), multiplication factor CLKFBOUT_MULT_F (8.000000) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device.

 

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pgigliotti_usac
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Registered: ‎10-22-2020

I opened the synthesized design and ran 

update_timing –full

 

This resolved the issue

View solution in original post

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pgigliotti_usac
Explorer
Explorer
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Registered: ‎10-22-2020

I opened the synthesized design and ran 

update_timing –full

 

This resolved the issue

View solution in original post

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pgigliotti_usac
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Registered: ‎10-22-2020

This worked once, but it is still an issue

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vanloc_tc1
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Registered: ‎12-03-2018

Hi @pgigliotti_usac,

Seem to be, I also have the same error with you. I tried Open Synthesized Design and Enter command "update_timing –full" at Tcl Console but it still exist. Any idea?

Error1:[DRC PDRC-34] MMCM_adv_ClkFrequency_div_no_dclk: The computed value 333.333 MHz (CLKIN1_PERIOD, net pll_clk3) for the VCO operating frequency of the MMCME2_ADV site MMCME2_ADV_X1Y0 (cell design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i) falls outside the operating range of the MMCM VCO frequency for this device (600.000 - 1200.000 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please run update_timing to update the MMCM settings. If that does not work, adjust either the input period CLKINx_PERIOD (24.000000), multiplication factor CLKFBOUT_MULT_F (8.000000) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device.

Error2:

  • [DRC PDRC-43] PLL_adv_ClkFrequency_div_no_dclk: The computed value 666.667 MHz (CLKIN1_PERIOD, net clk_out1) for the VCO operating frequency of the PLLE2_ADV site PLLE2_ADV_X1Y0 (cell design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i) falls outside the operating range of the PLL VCO frequency for this device (800.000 - 1600.000 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please adjust either the input period CLKINx_PERIOD (6.000000), multiplication factor CLKFBOUT_MULT_F (4) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device.
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