05-30-2019 04:38 AM
I am using xc7k325tffg900-2 fpga and i want interface a memory component GS81313LD18(QDR) using memory interface generator4.0(MIG). when i opened the mig for customization i didn't got the part which i have mentioned above.To generate a custom part I am unable to set the timing parameters as no options are available to do the same as the DDR MIG can provide the options to change the timing parameters and generate a custom part.
Can anyone help me how to validate that above mentioned memory componet can be used and if we can use what are the timing parameters need to be checked?
06-10-2019 10:08 AM
Hello @saikiran.k ,
Based on what I'm seeing here is this part of their SigmaQuad IIIe product line which is a bit different from their SigmaQuad II product line which matches the IP expectation for QDRII memories. The IP will never be able to support the GS81313LD18 because this is a Read Latency 3 device while the IP only supports a Read Latency of 2 or 2.5 depending on the configuration. You may be able to get something working by hacking the IP but this isn't supported by Xilinx and you'll have to work through this youself.
06-10-2019 12:35 PM
As I know GSI they provide FREE IP for customers using Xilinx FPGA. I have used them before. You can check their website. Have Fun !